IBM0625404GT3B IBM0625164GT3B
IBM0625804GT3B IBM06254B4GT3B
256Mb Double Data Rate Synchronous DRAM
Advance
Data Input (Write) (Timing Burst Length = 4)
tDSL
tDSH
DQS
tDH
tDS
DI n
DQ
tDH
tDS
DM
DI n = Data In for column n.
3 subsequent elements of data in are applied in programmed order following DI n.
Don’t Care
Data Output (Read) (Timing Burst Length = 4)
tDQSQ min
tDQSQ nom
DQS
tDQSQ max
tDQSQ nom
tDQSQ max
tDQSQ min
DQ
tDV
DQS and DQ
Data Valid Window
t
t
t
occurs when DQS is the earliest among DQS and DQ signals to transition.
occurs when DQS is the latest among DQS and DQ signals to transition.
, shown for reference, occurs when DQS transitions in the center among DQ signal transitions.
DQSQ max
DQSQ min
DQSQ nom
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
29L0011.E36997
10/99
Page 60 of 75
IBM [ IBM ]
