IBM0625164GT3B IBM0625404GT3B
IBM06254B4GT3B IBM0625804GT3B
Advance
256Mb Double Data Rate Synchronous DRAM
AC Operating Conditions (0 ˚C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
Symbol
Parameter/Condition
Input High (Logic 1) Voltage, DQ, DQS, and DM Signals
Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals
Input Differential Voltage, CK and CK Inputs
Min
+ 0.35
REF
Max
Unit
V
Notes
1, 2
V
V
IH(AC)
V
V
− 0.35
REF
V
1, 2
IL(AC)
ID(AC)
IX(AC)
V
V
0.7
V
+ 0.6
V
1, 2, 3
1, 2, 4
DDQ
Input Closing Point Voltage, CK and CK Inputs
0.5*V
− 0.2 0.5*V
+ 0.2
DDQ
V
DDQ
1. Input slew rate = 1V/ns.
2. Inputs are not recognized as valid until V
stabilizes.
REF
3. V is the magnitude of the difference between the input level on CK and the input level on CK.
ID
4. The value of V is expected to equal 0.5*V
of the transmitting device and must track variations in the DC level of the same.
DDQ
IX
I
Specifications and Conditions (0 ˚C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC
DD
Characteristics)
Symbol
Parameter/Condition
mA
Unit
mA
Notes
1, 2
Operating Current: one bank; active / precharge; t = t
; t = t
; DQ,
CK MIN
RC
RC MIN CK
I
I
DM, and DQS inputs changing twice per clock cycle; address and control inputs
changing once per clock cycle
TBD
DD0
Operating Current: one bank; active / read / precharge; Burst = 2; t = t
;
RC
RC MIN
CL = 2.5; t = t
; I = 0mA; address and control inputs changing once per
TBD
mA
1, 2
DD1
CK
CK MIN OUT
clock cycle
Precharge Power-Down Standby Current: all banks idle; power-down mode;
CKE ≤ V ; t = t
I
TBD
TBD
TBD
mA
mA
mA
1, 2
1, 2
1, 2
DD2P
IL MAX CK
CK MIN
Idle Standby Current: CS ≥ V
; all banks idle; CKE ≥ V
;
IH MIN
IH MIN
I
DD2N
t
= t
; address and control inputs changing once per clock cycle
CK
CK MIN
Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ V ; t = t
I
DD3P
IL MAX CK
CK MIN
Active Standby Current: one bank; active / precharge;CS ≥ V
;
IH MIN
I
CKE ≥ V
; t = t
; t = t ; DQ, DM, and DQS inputs changing
TBD
TBD
TBD
mA
mA
mA
1, 2
1, 2
1, 2
DD3N
IH MIN RC
RAS MAX CK
CK MIN
twice per clock cycle; address and control inputs changing once per clock cycle
Operating Current: one bank; Burst = 2; reads; continuous burst; address and
control inputs changing once per clock cycle; DQ and DQS outputs changing twice
per clock cycle; CL = 2.5; t = t
I
DD4R
; I
= 0mA
CK
CK MIN OUT
Operating Current: one bank; Burst = 2; writes; continuous burst; address and
control inputs changing once per clock cycle; DQ and DQS inputs changing twice
I
DD4W
per clock cycle; CL = 2.5; t = t
CK
CK MIN
I
I
Auto-Refresh Current: t = t
TBD
TBD
mA
mA
1, 2
DD5
RC
RFC MIN
Self-Refresh Current: CKE ≤ 0.2V
1, 2, 3
DD6
1. I specifications are tested after the device is properly initialized.
DD
2. Input slew rate = 1V/ns.
3. Enables on-chip refresh and address counters.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
29L0011.E36997
10/99
Page 55 of 75
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