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IBM0364804PT3B-360 参数 Datasheet PDF下载

IBM0364804PT3B-360图片预览
型号: IBM0364804PT3B-360
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 8MX8, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 72 页 / 1201 K
品牌: IBM [ IBM ]
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Discontinued (8/99 - last order; 12/99 - last ship)  
IBM0364804 IBM0364164  
IBM0364404 IBM03644B4  
64Mb Synchronous DRAM - Die Revision B  
AC Characteristics (TA = 0 to +70°C, VDD = 3.3V ± 0.3V)  
1. An initial pause of 200µs, with DQM and CKE held high, is required after power-up. A Precharge All Banks command must be given  
followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation.  
2. The Transition time is measured between VIH and VIL (or between VIL and VIH).  
3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH)  
in a monotonic manner.  
4. Load Circuit A: AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.40V crossover point  
5. Load Circuit A: AC measurements assume tT = 1.0 ns.  
6. Load Circuit B: AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.40V crossover point  
7. Load Circuit B: AC measurements assume tT = 1.2 ns.  
.
AC Output Load Circuits  
t
T
Vtt=1.4V  
V
IH  
50Ω  
Output  
1.4V  
t
t
CKH  
Clock  
Input  
CKL  
Zo = 50Ω  
V
IL  
50pF  
50pF  
t
SETUP  
AC Output Load Circuit (A)  
t
HOLD  
1.4V  
Output  
Zo = 50Ω  
t
OH  
t
AC  
t
AC Output Load Circuit (B)  
LZ  
1.4V  
Output  
Clock and Clock Enable Parameters  
-68  
-260  
Min.  
-360  
-10  
Symbol  
Parameter  
Units Notes  
Min.  
6.8  
12  
3
Max.  
1000  
1000  
6
Max.  
1000  
1000  
Min.  
7.4  
15  
3
Max.  
1000  
1000  
Min.  
10  
15  
3
Max.  
1000  
1000  
7
tCK3  
tCK2  
Clock Cycle Time, CAS Latency = 3  
Clock Cycle Time, CAS Latency = 2  
Clock Access Time, CAS Latency = 3  
Clock Access Time, CAS Latency = 2  
Clock Access Time, CAS Latency = 3  
Clock Access Time, CAS Latency = 2  
Clock High Pulse Width  
7.4  
10  
3
ns  
ns  
tAC3 (A)  
tAC2 (A)  
tAC3 (B)  
tAC2 (B)  
tCKH  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1
1
2
2
7
8
6
6
9
6
9
9
tCKL  
Clock Low Pulse Width  
3
3
3
3
tCES  
Clock Enable Set-up Time  
2
1.8  
0.8  
0
1.8  
0.8  
0
3
tCEH  
Clock Enable Hold Time  
1
1
tSB  
Power down mode Entry Time  
Transition Time (Rise and Fall)  
0
6.8  
10  
7.4  
10  
7.4  
10  
0
10  
10  
tT  
0.5  
0.5  
0.5  
0.5  
1. Access time is measured at 1.4V. See AC Characteristics, notes 1, 2, 3, 4, and 5 and load circuit A.  
2. Access time is measured at 1.4V. See AC Characteristics, notes 1, 2, 3, 6, and 7 and load circuit B.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
19L3264.E35855A  
1/28/99  
 
 
 
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