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IBM0364804PT3B-360 参数 Datasheet PDF下载

IBM0364804PT3B-360图片预览
型号: IBM0364804PT3B-360
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 8MX8, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 72 页 / 1201 K
品牌: IBM [ IBM ]
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Discontinued (8/99 - last order; 12/99 - last ship)  
IBM0364804 IBM0364164  
IBM0364404 IBM03644B4  
64Mb Synchronous DRAM - Die Revision B  
Operating, Standby, and Refresh Currents (TA = 0 to +70°C, VDD = 3.3V ± 0.3V)  
Speed  
Parameter  
Symbol  
Test Condition  
Units Notes  
mA 1, 2, 3  
-68  
75  
-260  
75  
-360  
75  
-10  
55  
1 bank operation  
tRC = tRC(min), tCK = min  
Active-Precharge command cycling  
without burst operation  
ICC1  
Operating Current  
CKE VIL(max), tCK = min,  
ICC2P  
1
1
1
1
1
1
1
1
mA  
mA  
1
1
CS =VIH(min)  
Precharge Standby Current in  
Power Down Mode  
CKE VIL(max),  
tCK = Infinity,  
ICC2PS  
CS =VIH(min)  
CKE VIH(min), tCK = min,  
ICC2N  
ICC2NS  
ICC3N  
ICC3P  
40  
5
35  
5
35  
5
25  
5
mA  
mA  
mA  
mA  
1, 5  
1, 7  
1, 5  
1, 6  
Precharge Standby Current in  
Non-Power Down Mode  
CS =VIH (min)  
CKE VIH(min), tCK = Infinity,  
CKE VIH(min), tCK = min,  
45  
7
40  
7
40  
7
30  
7
No Operating Current  
(Active state: 4 bank)  
CS =VIH (min)  
CKE VIL(max), tCK = min,  
tCK = min,  
Operating Current (Burst  
Mode)  
Read/ Write command cycling,  
Multiple banks active, gapless  
data,BL=4  
ICC4  
130  
120  
120  
90  
mA 1, 3, 4  
tCK = min, tRC = tRC(min)  
CBR command cycling  
ICC5  
Auto (CBR) Refresh Current  
Self Refresh Current  
145  
145  
145  
110  
mA  
1
SP  
LP  
1
1
1
1
mA  
ICC6  
CKE 0.2V  
1, 8  
µA  
400  
400  
400  
400  
1. Currents given are valid for a single device. The total current for a stacked device depends on the operation being performed on the  
other deck.  
2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input  
signals are changed up to three times during tRC(min).  
3. The specified values are obtained with the output open.  
4. Input signals are changed once during tCK(min).  
5. Input signals are changed once during three clock cycles.  
6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).  
7. Input signals are stable.  
8. SP: Standard power; LP: Low power.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
19L3264.E35855A  
1/28/99  
 
 
 
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