Discontinued (8/99 - last order; 12/99 - last ship)
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision B
Refresh Cycle
-68
-260
-360
-10
Symbol
Parameter
Units Notes
Min.
—
Max.
64
Min.
—
Max.
64
Min.
—
Max.
64
Min.
—
Max.
64
tREF
Refresh Period
Self Refresh Exit Time
ms
ns
1
tSREX
10
10
10
10
1. 4096 auto refresh cycles.
Write Cycle
-68
-260
-360
-10
Symbol
Parameter
Units
Min.
2
Max.
Min.
Max.
Min.
1.8
0.8
1
Max.
Min.
3
Max.
—
tDS
tDH
tDPL
tDQW
Data In Set-up Time
Data In Hold Time
—
—
—
—
1.8
0.8
1
—
—
—
—
—
—
—
—
ns
ns
1
1
—
Data input to Precharge
DQM Write Mask Latency
1
1
—
CLK
CLK
0
0
0
0
—
Clock Frequency and Latency
Symbol
fCK
Parameter
Clock Frequency
-68
-260
100
10
3
-360
-10
Units
147
6.8
3
83
12
2
135
100
10
2
135
100
10
3
66
15
2
100
66
MHz
ns
tCK
Clock Cycle Time
7.4
3
7.4
3
10
3
3
3
9
6
1
4
2
1
0
0
2
1
15
2
2
2
6
4
1
3
2
1
0
0
2
1
tAA
CAS Latency
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
tRP
Precharge Time
3
2
3
2
2
3
2
2
tRCD
tRC
RAS to CAS Delay
3
2
3
2
2
3
2
2
Bank Cycle Time
10
7
6
9
7
7
9
7
5
tRAS
tDPL
tDAL
tRRD
tCCD
tWL
Minimum Bank Active Time
Data In to Precharge
Data In to Active/Refresh
Bank to Bank Delay Time
CAS to CAS Delay Time
Write Latency
4
6
5
5
6
5
3
1
1
1
1
1
1
1
1
4
3
4
3
3
4
3
3
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
tDQW
tDQZ
tCSL
DQM Write Mask Latency
DQM Data Disable Latency
Clock Suspend Latency
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L3264.E35855A
1/28/99
Page 44 of 72
IBM [ IBM ]
