Discontinued (8/99 - last order; 12/99 - last ship)
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision B
Burst write operations will be terminated by the Precharge command. The last write data that will be properly
stored in the device is that write data that is presented to the device a number of clock cycles prior to the Pre-
charge command equal to the Data-in to Precharge delay, tDPL
.
Precharge Termination of a Burst Write
(Burst Length = 8, CAS Latency =2, 3)
T6 T7 T8
T0
T1
T2
T3
T4
T5
CLK
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
NOP
WRITE Ax0
COMMAND
DQM
t
DPL
CAS latency = 2
tCK2, DQs
DIN Ax0
DIN Ax0
DIN Ax1
DIN Ax1
DIN Ax2
t
DPL
CAS latency = 3
tCK3, DQs
DIN Ax2
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L3264.E35855A
1/28/99
Page 27 of 72
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