Discontinued (8/99 - last order; 12/99 - last ship)
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision B
Burst Write with Auto-Precharge Interrupted by Read
(Burst Length = 4, CAS Latency = 3)
T6 T7 T8
T0
T1
T2
T3
T4
T5
CLK
WRITE A
NOP
READ B
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Auto-Precharge
t
*
*
RP
CAS latency = 3
tCK3, DQs
DIN A0
DIN A1
DIN A2
DOUT B0
DOUT B1
DOUT B2
Begin Auto-Precharge A
Bank A can be reactivated at completion of t
RP
*
For -360/-260, tCK3 = 10; tRP = 2
*
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Com-
mand is triggered when CS, RAS, and WE are low and CAS is high at the rising edge of the clock. The Pre-
charge Command can be used to precharge each bank separately or all banks simultaneously. Three
address bits—A10, A12, and A13—are used to define which bank(s) is to be precharged when the command
is issued.
Bank Selection for Precharge by Address Bits
A10
LOW
HIGH
Bank Select
BS0, BS1
Precharged Bank(s)
Bank defined by BS0, BS1 only
All Banks
DON’T CARE
For read cycles, the Precharge Command may be applied (CAS latency - 1) clocks prior to the last data out-
put. For write cycles, a delay must be satisfied from the start of the last burst write cycle until the Precharge
Command can be issued. This delay is known as tDPL, Data-in to Precharge delay.
After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write
access can be executed. The delay between the Precharge Command and the Activate Command must be
greater than or equal to the Precharge time (tRP).
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L3264.E35855A
1/28/99
Page 24 of 72
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