Discontinued (8/99 - last order; 12/99 - last ship)
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision B
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The
SDRAM automatically enters the precharge operation after a delay from the last burst write cycle referred to
as Data-in to Precharge delay, tDPL. The bank undergoing auto-precharge can not be reactivated until tDPL and
tRP are satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tDPL + tRP).
Burst Write with Auto-Precharge
(Burst Length = 2, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
BANK A
ACTIVE
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Auto-Precharge
t
t
RP
DPL
CAS latency = 2
tCK2, DQs
DIN A0
DIN A0
DIN A1
t
*
*
t
RP
DPL
CAS latency = 3
tCK3, DQs
DIN A1
*
Begin Auto-Precharge
Bank can be reactivated at completion of t
RP
*
For -360/-260, tCK3 = 10; tRP = 2
*
Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command
to the same bank. It can be interrupted by a Read or Write Command to a different bank, however. The pre-
charge function will begin with the new command. The bank may be reactivated after tRP is satisfied.
Burst Write with Auto-Precharge Interrupted by Write
(Burst Length = 4, CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
BANK A
ACTIVE
WRITE A
NOP
NOP
WRITE B
DIN B0
NOP
NOP
NOP
NOP
COMMAND
Auto-Precharge
t
*
t
*
RCD
RP
*
DIN B3
CAS latency = 3
tCK3, DQs
DIN A0
DIN A1
DIN B1
DIN B2
Begin Auto-Precharge A
*
For -360/-260, tCK3 = 10: tRP, tRCD= 2
Bank A can be reactivated at completion of t
RP
*
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L3264.E35855A
1/28/99
Page 23 of 72
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