Discontinued (8/99 - last order; 12/99 - last ship)
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision B
Burst Read followed by the Precharge Command
(Burst Length = 4, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ Ax0
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
COMMAND
t
RP
*
CAS latency = 2
DOUT Ax0
DOUT Ax1
DOUT Ax2
DOUT Ax3
tCK2, DQs
Bank A can be reactivated at completion of t
RP
*
Burst Write followed by the Precharge Command
(Burst Length = 2, CAS Latency = 2)
T6 T7 T8
T0
T1
T2
T3
T4
T5
CLK
Activate
Bank Ax
NOP
NOP
Precharge A
NOP
NOP
NOP
NOP
WRITE Ax0
COMMAND
t
t
DPL
RP
t
DAL
*
CAS latency = 2
tCK2, DQs
DIN Ax0
DIN Ax1
Bank can be reactivated at completion of tDAL
*
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L3264.E35855A
1/28/99
Page 25 of 72
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