欢迎访问ic37.com |
会员登录 免费注册
发布采购

IBM0316809CT3D-10 参数 Datasheet PDF下载

IBM0316809CT3D-10图片预览
型号: IBM0316809CT3D-10
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 2MX8, 8ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 120 页 / 1896 K
品牌: IBM [ IBM ]
 浏览型号IBM0316809CT3D-10的Datasheet PDF文件第44页浏览型号IBM0316809CT3D-10的Datasheet PDF文件第45页浏览型号IBM0316809CT3D-10的Datasheet PDF文件第46页浏览型号IBM0316809CT3D-10的Datasheet PDF文件第47页浏览型号IBM0316809CT3D-10的Datasheet PDF文件第49页浏览型号IBM0316809CT3D-10的Datasheet PDF文件第50页浏览型号IBM0316809CT3D-10的Datasheet PDF文件第51页浏览型号IBM0316809CT3D-10的Datasheet PDF文件第52页  
Discontinued (12/98 - last order; 9/99 last ship)  
IBM0316409C IBM0316809C IBM0316169C  
IBM03164B9C  
16Mb Synchronous DRAM-Die Revision D  
AC Characteristics (T = 0 to +70˚C, V = 3.3V ± 0.3V)  
A
DD  
1. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must be given followed by a minimum of  
two Auto (CBR) Refresh cycles before the Mode Register Set operation can begin.  
2. The Transition time is measured between VIH and VIL (or between VIL and VIH).  
3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH)  
in a monotonic manner.  
4. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.40V crossover point.  
5. AC measurements assume tT=1.0 ns.  
tT  
VIH  
1.4V  
Clock  
VIL  
Vtt=1.4V  
tSETUP  
50Ω  
tHOLD  
Output  
Z = 50Ω  
o
50pF  
1.4V  
Input  
AC Output Load Circuit  
tOH  
tAC  
tLZ  
1.4V  
Output  
Clock and Clock Enable Parameters  
-80  
-360  
Max.  
100MHz 10 100MHz ns  
-10  
Symbol  
Parameter  
Units Notes  
Min.  
Max.  
Min.  
10  
15  
3
Min. Max.  
tCK3  
tCK2  
tCK1  
tAC3  
tAC2  
tAC1  
tCKH  
tCKL  
tCES  
tCEH  
tCESP  
tT  
Clock Cycle Time,CAS Latency=3  
Clock Cycle Time,CAS Latency=2  
Clock Cycle Time,CAS Latency=1  
Clock Access Time,CAS Latency=3  
Clock Access Time,CAS Latency=2  
Clock Access Time,CAS Latency=1  
Clock High Pulse Width  
8
12  
3
125MHz  
83MHz  
66MHz  
15  
30  
3.5  
3.5  
3
66MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
33MHz  
8
6
5.5  
9
1, 2  
1, 2  
1, 2  
3
7
9
27  
Clock Low Pulse Width  
3
3
3
Clock Enable Set-up Time  
2
2
Clock Enable Hold Time  
1
1
1
CKE Set-up Time (Power down mode)  
Transition Time (Rise and Fall)  
2
2
3
1
30  
1
30  
1
30  
1. Access time is measured at 1.4V. See AC Characteristics: notes 1,2,3,4,5 and load circuit.  
2. Access time is measured assuming a clock rise time of 1 ns. If clock rise time is longer than 1 ns, then (trise/2-0.5)ns should be  
added to the parameter.  
3. Assumes clock rise and fall times are equal to 1 ns. If rise or fall time exceeds 1 ns, then other AC parameters under consider-  
ation should be compensated by an additional [(trise+tfall)/2-1]ns.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
08J3348.E35853  
5/98  
 
 
 
 复制成功!