Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Common Parameters
-80
-360
-10
Symbol
Parameter
Units
Min.
2
Max.
—
Min.
2
Max.
—
Min.
3
Max.
—
tCS
tCH
Command Setup Time
ns
ns
Command Hold Time
1
—
1
—
1
—
tAS
Address and Bank Select Set-up Time
Address and Bank Select Hold Time
RAS to CAS Delay
2
—
2
—
3
—
ns
tAH
1
—
1
—
1
—
ns
tRCD
tRC
tRAS
tRP
tRRD
tCCD
24
72
48
24
16
1
—
20
70
50
20
20
1
—
30
90
60
30
20
1
—
ns
Bank Cycle Time
120K
120K
—
120K
120K
—
120K
120K
—
ns
Active Command Period
Precharge Time
ns
ns
Bank to Bank Delay Time
CAS to CAS Delay Time (Same Bank)
—
—
—
ns
—
—
—
CLK
Refresh Cycle
-80
-360
-10
Symbol
Parameter
Units Notes
Min.
—
Max.
Min.
Max.
Min.
—
Max.
tREF
Refresh Period
Self Refresh Exit Time
64
—
64
64
ms
ns
1, 2
3
10ns +
tRC
10ns +
10ns +
tRC
tSREX
—
—
—
tRC
1. 4096 cycles.
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-
up” the device.
3. Self Refresh Exit is an asynchronous operation. Self refresh exit is accomplished by starting the clock (CLK) and then asserting
CKE high. During the exit time (tSREX), no commands may be issued until tRC is satisfied and CKE must remain high. It is recom-
mended to hold CS high during the self refresh exit time, but NOP commands may be issued with each rising clock edge during this
period as an alternative. To prevent erroneous exit of self refresh operation, a glitch suppressor circuit is incorporated into the CKE
receiver. If CKE is asserted high (system noise) for less than 10ns (approximately), then the device will not exit self refresh opera-
tion.
Read Cycle
-80
-360
Max.
-10
Symbol
Parameter
Units Notes
Min.
2.5
2.5
2.5
2.5
—
Max.
—
—
6
Min.
3
Min.
3
Max.
—
—
8
tOH
tLZ
Data Out Hold Time
—
—
5.5
8
ns
ns
1
Data Out to Low Impedance Time
2.5
2.5
2.5
—
3
tHZ3
tHZ2
tHZ1
tDQZ
Data Out to High Impedance Time,CL= 3
Data Out to High Impedance Time,CL= 2
Data Out to High Impedance Time,CL= 1
DQM Data Out Disable Latency
3
ns
2
2
2
7
3
8
ns
—
—
—
—
3
15
—
ns
2
2
2
CLK
1. -360: 50pf load.
2. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Page 49 of 120
IBM [ IBM ]
