Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ
contention.
Burst Read with Auto-precharge Interrupted by Write (Burst Length = 8, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WRITE B
DOUT B
COMMAND
Auto-Precharge
tRP+tDPL
*
CAS latency = 2
t
CK2, DQs
DOUT A
DOUT B
DOUT B
DOUT B
DOUT B
4
0
0
1
2
3
DQM
Begin Auto-precharge A
Bank A can be reactivated at completion of t
t
RP + DPL
*
If A10 is high when a Write Command is issued, the Write with auto-precharge function is initiated. The bank
undergoing auto-precharge can not be reactivated until tDPL and tRP are satisfied. This is referred to as tDAL,
Data-in to Active delay (tDAL= tDPL + tRP), and is an asynchronous delay time during auto-precharge.
Burst Write with Auto-Precharge (Burst Length = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Auto-Precharge
tDAL
tCK2
DQs
DIN A
DIN A
DIN A
DIN A
0
1
*
tDAL
tCK3
DQs
0
1
*
*
Bank can be reactivated after completion of tDAL
.
For Auto-Precharge, tDAL is an asynchronous delay
which may complete prior to a clock edge, depending
on tRP tDPL
until the rising clock edge following the delay.
tCK. The bank cannot be reactivated
Begin Auto-precharge.
,
and
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
Page 23 of 120
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