Discontinued (12/98 - last order; 9/99 last ship)
IBM0316409C IBM0316809C IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
Power On and Initialization
The default power on state of the mode register is supplier specific and may be undefined. The following
power on and initialization sequence guarantees the device is preconditioned to each user’s specific needs.
Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined man-
ner. During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage no
later than any of the input signal voltages. The power on voltage must not exceed VDD+0.3V on any of the
input pins or VDD supplies. After power on, an initial pause of 100µs is required followed by a precharge of
both banks using the precharge command. To reduce the possibility of data contention on the DQ bus during
power on, it is recommended that the DQM pin(s) be held high during the initial pause period. Once both
banks have been precharged, a minimum of two Auto Refresh cycles (CBR) must occur before the Mode
Register can be programmed. Failure to follow these steps may lead to unpredictable start-up modes.
Programming the Mode Register
For application flexibility, CAS latency, burst length, burst sequence, and operation type are user defined vari-
ables and must be programmed into the SDRAM Mode Register with a single Mode Register Set Command.
Contents of the Mode Register can be altered by re-executing the Mode Register Set Command. If the user
chooses to modify only a subset of the Mode Register variables, all variables must be redefined when the
Mode Register Set Command is issued.
After initial power up, the Mode Register Set Command must be issued before read or write cycles may
begin. Both banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of
RAS, CAS, CS and WE at the positive edge of the clock. The address input data during this cycle defines the
parameters to be set as shown in the Mode Register Operation table. A new command may be issued on the
second clock following the mode register set command.
CAS Latency
CAS latency is a parameter that is used to define the delay from when a Read Command is registered on a
rising clock edge to when the data from that Read Command becomes available at the outputs. CAS latency
is expressed in terms of clock cycles and can be programmed to a value of 1, 2, or 3 cycles. The value of
CAS latency is determined by the speed grade of the device and the clock frequency that is used in the appli-
cation. A table showing the relationship between the CAS latency, speed grade, and clock frequency appears
in the Electrical Characteristics section of this document. Once the appropriate CAS latency has been
selected it must be programmed into the mode register after power up. For an explanation of this procedure,
see Programming the Mode Register in the previous section.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
08J3348.E35853
5/98
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