IBM0316809C IBM0316409C
IBM0316169C
16Mbit Synchronous DRAM
Timing Diagrams
Page
AC Parameters for Write Timing...............................................................................................................42
AC Parameters for Read Timing...............................................................................................................43
Mode Register Set ....................................................................................................................................44
Power on Sequence and Auto Refresh (CBR)..........................................................................................45
Clock Suspension During a Burst Read (Using CKE)
CAS Latency = 1...............................................................................................................46
CAS Latency = 2...............................................................................................................47
CAS Latency = 3...............................................................................................................48
Clock Suspension During a Burst Write (Using CKE)
CAS Latency = 1...............................................................................................................49
CAS Latency = 2...............................................................................................................50
CAS Latency = 3...............................................................................................................51
Power Down Mode and Clock Mask.........................................................................................................52
Auto Refresh (CBR)..................................................................................................................................53
Self Refresh (Entry and Exit) ....................................................................................................................54
Random Column Read (Page within same Bank)
CAS Latency = 1...............................................................................................................55
CAS Latency = 2...............................................................................................................56
CAS Latency = 3...............................................................................................................57
Random Column Write (Page within same Bank)
CAS Latency = 1...............................................................................................................58
CAS Latency = 2...............................................................................................................59
CAS Latency = 3...............................................................................................................60
Random Row Read (Interleaving Banks)
CAS Latency = 1...............................................................................................................61
CAS Latency = 2...............................................................................................................62
CAS Latency = 3...............................................................................................................63
Random Row Write (Interleaving Banks)
CAS Latency = 1...............................................................................................................64
CAS Latency = 2...............................................................................................................65
CAS Latency = 3...............................................................................................................66
Read And Write Cycle
CAS Latency = 1...............................................................................................................67
CAS Latency = 2...............................................................................................................68
CAS Latency = 3...............................................................................................................69
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
07H3997
SA14-4711-02
Revised 05/96
Page 38 of 100
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