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IBM0316809CT3-11 参数 Datasheet PDF下载

IBM0316809CT3-11图片预览
型号: IBM0316809CT3-11
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 2MX8, 10ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 100 页 / 1216 K
品牌: IBM [ IBM ]
 浏览型号IBM0316809CT3-11的Datasheet PDF文件第33页浏览型号IBM0316809CT3-11的Datasheet PDF文件第34页浏览型号IBM0316809CT3-11的Datasheet PDF文件第35页浏览型号IBM0316809CT3-11的Datasheet PDF文件第36页浏览型号IBM0316809CT3-11的Datasheet PDF文件第38页浏览型号IBM0316809CT3-11的Datasheet PDF文件第39页浏览型号IBM0316809CT3-11的Datasheet PDF文件第40页浏览型号IBM0316809CT3-11的Datasheet PDF文件第41页  
IBM0316409C IBM0316809C  
IBM0316169C  
16Mbit Synchronous DRAM  
Write Cycle  
-10  
-11  
-12  
-13  
Symbol  
Parameter  
Data In Set-up Time  
Units  
Notes  
Min. Max. Min. Max. Min. Max. Min. Max.  
tDS  
tDH  
3
1
3
1
3.5  
1.5  
3.5  
1.5  
ns  
ns  
Data In Hold Time  
1CLK  
+10  
1CLK  
+11  
1CLK  
+12  
1CLK  
+13  
tDPL3  
Data input to Precharge, CAS Latency = 3  
ns  
tDPL2  
tDPL1  
Data input to Precharge, CAS Latency = 2  
Data input to Precharge, CAS Latency = 1  
15  
15  
16.5  
16.5  
18  
18  
19.5  
19.5  
ns  
ns  
2CLK  
+30  
2CLK  
+33  
2CLK  
+36  
2CLK  
+39  
tDAL3  
tDAL2  
tDAL1  
tDQW  
1.  
Data In to Active/Refresh, CAS Latency = 3  
Data In to Active/Refresh, CAS Latency = 2  
ns  
ns  
1
1
1
1CLK  
+30  
1CLK  
+33  
1CLK  
+36  
1CLK  
+39  
1CLK  
+30  
1CLK  
+33  
1CLK  
+36  
1CLK  
+39  
Data In to Active/Refresh, CAS Latency = 1  
DQM Write Mask Latency  
ns  
0
0
0
0
CLK  
t
DAL is equivalent to tDPL + tRP.  
Clock Frequency and Latency  
Speed Sort  
Symbol  
Parameter  
Units  
Notes  
-10  
-11  
-12  
56  
18  
2
-13  
fCK  
tCK  
Clock Frequency  
Clock Cycle Time  
CAS Latency  
100 66  
33  
91  
61  
30  
83  
12  
3
28  
36  
1
77  
51  
26  
MHz  
ns  
10  
3
15  
2
30  
1
11 16.5 33  
13 19.5 39  
tAA  
tCK  
tCK  
tCK  
tCK  
tCK  
µs  
3
3
6
8
5
2
2
4
5
3
1
1
2
3
2
3
3
6
8
5
2
2
4
5
3
1
1
2
3
2
tRCD  
tRL  
RAS to CAS Delay  
RAS Latency  
3
2
1
3
2
1
6
4
2
6
4
2
tRC  
Bank Cycle Time  
Minimum Bank Active Time  
8
5
3
8
5
3
tRAS  
tRAS  
tRP  
5
3
2
5
3
2
Maximum Bank Active Time 120 120 120 120 120 120 120 120 120 120 120 120  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
Precharge Time  
3
2
5
3
1
0
0
2
1
2
1
3
2
1
0
0
2
1
1
1
2
1
1
0
0
2
1
3
2
5
3
1
0
0
2
1
2
1
3
2
1
0
0
2
1
1
1
2
1
1
0
0
2
1
3
2
5
3
1
0
0
2
1
2
1
3
2
1
0
0
2
1
1
1
2
1
1
0
0
2
1
3
2
5
3
1
0
0
2
1
2
1
3
2
1
0
0
2
1
1
1
2
1
1
0
0
2
1
tDPL  
tDAL  
tRRD  
tCCD  
tWL  
Data In to Precharge  
Data In to Active/Refresh  
Bank to Bank Delay Time  
CAS to CAS Delay Time  
Write Latency  
tDQW  
tDQZ  
tCSL  
DQM Write Mask Latency  
DQM Data Disable Latency  
Clock Suspend Latency  
©IBM Corporation, 1996. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
07H3997  
SA14-4711-02  
Revised 05/96  
Page 37 of 100  
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