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IBM0316809CT3-11 参数 Datasheet PDF下载

IBM0316809CT3-11图片预览
型号: IBM0316809CT3-11
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 2MX8, 10ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 100 页 / 1216 K
品牌: IBM [ IBM ]
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IBM0316409C IBM0316809C  
IBM0316169C  
16Mbit Synchronous DRAM  
Timing Diagrams  
Page  
Interleaved Column Read Cycle  
CAS Latency = 1............................................................................................................... 70  
CAS Latency = 2............................................................................................................... 71  
CAS Latency = 3............................................................................................................... 72  
Interleaved Column Write Cycle  
CAS Latency = 1............................................................................................................... 73  
CAS Latency = 2............................................................................................................... 74  
CAS Latency = 3............................................................................................................... 75  
Auto Precharge after a Read Burst  
CAS Latency = 1............................................................................................................... 76  
CAS Latency = 2............................................................................................................... 77  
CAS Latency = 3............................................................................................................... 78  
Auto Precharge after a Write Burst  
CAS Latency = 1............................................................................................................... 79  
CAS Latency = 2............................................................................................................... 80  
CAS Latency = 3............................................................................................................... 81  
Full Page Read Cycle  
CAS Latency = 1............................................................................................................... 82  
CAS Latency = 2............................................................................................................... 83  
CAS Latency = 3............................................................................................................... 84  
Full Page Write Cycle  
CAS Latency = 1............................................................................................................... 85  
CAS Latency = 2............................................................................................................... 86  
CAS Latency = 3............................................................................................................... 87  
Byte Write Operation ................................................................................................................................ 88  
Burst Read and Single Write Operation ................................................................................................... 89  
Full Page Burst Read and Single Write Operation ................................................................................... 90  
Random Row Read (Interleaving Banks) ................................................................................................. 91  
Full Page Random Column Read............................................................................................................. 92  
Full Page Random Column Write............................................................................................................. 93  
Precharge Termination of a Burst  
CAS Latency = 1............................................................................................................... 94  
CAS Latency = 2............................................................................................................... 95  
CAS Latency = 3............................................................................................................... 96  
CS Function (Only CS signal needs to be asserted at minimum rate) ..................................................... 97  
©IBM Corporation, 1996. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
07H3997  
SA14-4711-02  
Revised 05/96  
Page 39 of 100  
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