IBM0316409C IBM0316809C
IBM0316169C
16Mbit Synchronous DRAM
AC Characteristics (T = 0 to +70˚C, V = 3.3V ± 0.3V)
A
DD
1. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must be given followed by a minimum of
two Auto (CBR) Refresh cycles before the Mode Register Set operation can begin.
2. AC timing tests have VIL = 0.8V and VIH = 2.0V with the timing referenced to the 1.40V crossover point.
tT
2.0V
1.4V
0.8V
Clock
Input
tSETUP
tHOLD
1.4V
tOH
tAC
tLZ
1.4V
Output
3. The Transition time is measured between VIH and VIL (or between VIL and VIH).
4. AC measurements assume tT=1ns.
5. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
Clock and Clock Enable Parameters
-10
Max.
10 100MHz 11
-11
Max.
91MHz
66MHz 16.5 61MHz
-12
Max.
83MHz
-13
Max.
77MHz
Symbol
Parameter
Units Notes
Min.
Min.
Min.
12
18
36
—
—
—
4
Min.
13
tCK3
tCK2
tCK1
tAC3
tAC2
tAC1
tCH
Clock Cycle Time, CAS Latency = 3
Clock Cycle Time, CAS Latency = 2
Clock Cycle Time, CAS Latency = 1
Clock Access Time, CAS Latency = 3
Clock Access Time, CAS Latency = 2
Clock Access Time, CAS Latency = 1
Clock High Pulse Width
ns
ns
ns
15
30
—
—
—
3.5
3.5
3
56MHz 19.5 51MHz
33MHz
9
33
—
—
—
3.5
3.5
3
30MHz
10
28MHz
11
39
—
—
—
5
26MHz
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
2
12
27
—
13.5
30
15
16.5
36
33
—
—
—
tCL
Clock Low Pulse Width
—
—
4
—
5
—
tCKS
tCKH
tCKSP
tT
Clock Enable Set-up Time
—
—
3.5
1.5
3.5
1
—
3.5
1.5
3.5
1
—
Clock Enable Hold Time
1
—
1
—
—
—
CKE Set-up Time (Power down mode)
Transition Time (Rise and Fall)
3
—
3
—
—
—
1
30
1
30
30
30
1. 50pF Load.
2. 80pF Load.
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
07H3997
SA14-4711-02
Revised 05/96
Page 35 of 100
IBM [ IBM ]
