IBM0316409C IBM0316809C
IBM0316169C
16Mbit Synchronous DRAM
Method 2: CAS latency = 3, Burst Length = 1, 2, 4, or 8
If the CAS latency is 3 and the burst length is not full page, then a Burst Read operation can be interrupted by
a Write command provided that the Write command occurs after a minimum interval of [burst length +1]
cycles.
Read to Write Interval: Burst Length = 4, CAS latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Minimum delay between the Read and Write Commands = 4+1 = 5 cycles
DQM
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
NOP
COMMAND
DIN B
0
DIN B
DIN B
2
DOUT A
DQ’s
1
0
Must be Hi-Z before
the Write Command
: “H” or “L”
If the CAS latency is 3 and the burst length is full page, then a Burst Read operation can never be interrupted
by a Write command. In this situation, the Burst Read operation must be interrupted by a Burst Stop
Command before a Write operation can be issued to the open bank.
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
07H3997
SA14-4711-02
Revised 05/96
Page 15 of 100
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