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HY29F002TT-55 参数 Datasheet PDF下载

HY29F002TT-55图片预览
型号: HY29F002TT-55
PDF下载: 下载PDF文件 查看货源
内容描述: 2兆位( 256K ×8 ) , 5伏只,闪存 [2 Megabit (256K x 8), 5 Volt-only, Flash Memory]
分类和应用: 闪存
文件页数/大小: 38 页 / 381 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
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HY29F002T  
Table 3. HY29F002T Bus Operations Requiring High Voltage 1, 2  
Operation 3  
CE# OE# WE# RESET# A[17:13] A[9] A[6] A[1] A[0] DQ[7:0]  
Sector Protect  
L
VID  
VID  
X
X
H
H
SA 4  
VID  
VID  
X
X
X
X
X
X
X
X
Sector Unprotect  
VID  
X
Temporary Sector  
Unprotect  
X
X
X
VID  
X
X
X
X
X
X
Manufacturer Code  
Device Code  
L
L
L
L
H
H
H
H
X
X
VID  
VID  
L
L
L
L
L
0xAD  
0xB0  
0x00  
H
Sector  
Unprotected  
Protected  
Protection  
Verification  
L
L
H
H
SA 4  
VID  
L
H
L
0x01  
Notes:  
1. L = VIL, H = VIH, X = Dont Care. See DC Characteristics for voltage levels.  
2. Address bits not specified are Dont Care.  
3. See text for additional information.  
4. SA = sector address. See Table 1.  
The Device Commandssection of this document  
provides details on the specific device commands  
implemented in the HY29F002T.  
The device requires standard access time (tCE) for  
read access when the device is in either of the  
standby modes, before it is ready to read data. If  
the device is deselected during erasure or pro-  
gramming, it continues to draw active current until  
the operation is completed.  
Output Disable Operation  
When the OE# input is at VIH, output data from the  
device is disabled and the data bus pins are placed  
in the high impedance state.  
Hardware Reset Operation  
The RESET# pin provides a hardware method of  
resetting the device to reading array data. When  
the RESET# pin is driven Low for the minimum  
specified period, the device immediately termi-  
nates any operation in progress, tri-states the data  
bus pins, and ignores all read/write commands for  
the duration of the RESET# pulse. The device also  
resets the internal state machine to reading array  
data. If an operation was interrupted by the as-  
sertion of RESET#, it should be reinitiated once  
the device is ready to accept another command  
sequence to ensure data integrity.  
Standby Operation  
When the system is not reading from or writing to  
the HY29F002T, it can place the device in the  
Standby mode. In this mode, current consump-  
tion is greatly reduced, and the data bus outputs  
are placed in the high impedance state, indepen-  
dent of the OE# input. The Standby mode can  
invoked using two methods.  
The device enters the CE# CMOS Standby mode  
if the CE# and RESET# pins are both held at VCC  
± 0.5V. Note that this is a more restricted voltage  
range than VIH. If both CE# and RESET# are held  
High, but not within VCC ± 0.5V, the device will be  
in the CE# TTL Standby mode, but the standby  
current will be greater.  
Current is reduced for the duration of the RESET#  
pulse as described in the Standby Operation sec-  
tion above.  
If RESET# is asserted during a program or erase  
operation, the internal reset operation is completed  
within a time of tREADY (during Automatic Algo-  
rithms). The system can perform a read or write  
operation after waiting for a minimum of tREADY or  
until tRH after the RESET# pin returns High, which-  
ever is longer. If RESET# is asserted when a pro-  
gram or erase operation is not executing, the re-  
The device enters the RESET# CMOS Standby  
mode when the RESET# pin is held at VSS ± 0.5V.  
If RESET# is held Low but not within VSS ± 0.5V,  
the HY29F002T will be in the RESET# TTL  
Standby mode, but the standby current will be  
greater. See Hardware Reset Operation section  
for additional information on the reset operation.  
Rev. 4.1/May 01  
6