HY29F002T
PIN CONFIGURATIONS
A[11]
A[9]
1
2
3
4
5
6
7
32
31
30
29
28
27
26
OE#
A[10]
CE#
A[8]
A[13]
A[14]
A[17]
WE#
DQ[7]
DQ[6]
DQ[5]
DQ[4]
VC C
RESET#
8
9
25
24
DQ[3]
VSS
TSOP32
A[16]
A[15]
10
11
23
22
DQ[2]
DQ[1]
A[12]
A[7]
12
13
21
20
DQ[0]
A[0]
A[6]
A[5]
A[4]
14
15
16
19
18
17
A[1]
A[2]
A[3]
4
3
2
1 32 31 30
A[7]
A[6]
5
6
29
28
27
26
25
24
23
22
21
A[14]
A[13]
A[8]
A[5]
7
A[4]
8
A[9]
A[3]
9
A[11]
OE#
A[10]
CE#
PLCC32
A[2]
10
11
12
13
A[1]
A[0]
DQ[0]
DQ[7]
14 15 16 17 18 19 20
CONVENTIONS
Whenever a signal is separated into numbered
bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of
bits may also be shown collectively, e.g., as
DQ[7:0].
Unless otherwise noted, a positive logic (active
High) convention is assumed throughout this docu-
ment, whereby the presence at a pin of a higher,
more positive voltage (nominally 5VDC) causes
assertion of the signal. A ‘#’ symbol following the
signal name, e.g., RESET#, indicates that the sig-
nal is asserted in a Low state (nominally 0 volts).
The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .
. . , E, F) indicates a number expressed in hexa-
decimal notation. The designation 0bXXXX indi-
cates a number expressed in binary notation (X =
0, 1).
Rev. 4.1/May 01
3
HYNIX [ HYNIX SEMICONDUCTOR ]
