HY29F002T
Table 2. HY29F002T Normal Bus Operations1
Operation
CE#
OE#
L
WE#
H
RESET#
A[17:0]
DQ[7:0]
Read
Write
L
H
AIN
AIN
X
DOUT
DIN
L
H
L
H
Output Disable
L
H
H
H
High-Z
High-Z
High-Z
High-Z
High-Z
CE# TTL Standby
H
X
X
H
VCC ± 0.5V
L
X
CE# CMOS Standby
Hardware Reset (TTL Standby)
Hardware Reset (CMOS Standby)
Notes:
V
CC ± 0.5V
X
X
X
X
X
X
X
X
X
X
VSS ± 0.5V
X
1. L = VIL, H = VIH, X = Don’t Care, DOUT = Data Out, DIN = Data In. See DC Characteristics for voltage levels.
BUS OPERATIONS
data from or program data into any sector of
memory that is not marked for erasure. If the host
attempts to read from an address within an erase-
suspended sector, or while the device is perform-
ing an erase or byte program operation, the de-
vice outputs status data instead of array data. After
completing a programming operation in the Erase
Suspend mode, the system may once again read
array data with the same exceptions noted above.
After completing an internal program or internal
erase algorithm, the HY29F002T automatically re-
turns to the read array data mode.
Device bus operations are initiated through the
internal command register, which consists of sets
of latches that store the commands, along with
the address and data information, if any, needed
to execute the specific command. The command
register itself does not occupy any addressable
memory location. The contents of the command
register serve as inputs to an internal state ma-
chine whose outputs control the operation of the
device. Table 2 lists the normal bus operations,
the inputs and control levels they require, and the
resulting outputs. Certain bus operations require
a high voltage on one or more device pins. Those
are described in Table 3.
The host must issue a hardware reset or the soft-
ware reset command (see Command Definitions)
to return a sector to the read array data mode if
DQ[5] goes high during a program or erase cycle,
or to return the device to the read array data mode
while it is in the Electronic ID mode.
Read Operation
Data is read from the HY29F002T by using stan-
dard microprocessor read cycles while placing the
address of the byte to be read on the device’s
address inputs, A[17:0]. As shown in Table 2, the
host system must drive the CE# and OE# inputs
Low and drive WE# High for a valid read opera-
tion to take place. The device outputs the speci-
fied array data on DQ[7:0].
Write Operation
Certain operations, including programming data
and erasing sectors of memory, require the host
to write a command or command sequence to the
HY29F002T. Writes to the device are performed
by placing the byte address on the device’s ad-
dress inputs while the data to be written is input
on DQ[7:0]. The host system must drive the CE#
and WE# pins Low and drive OE# High for a valid
write operation to take place. All addresses are
latched on the falling edge of WE# or CE#, which-
ever happens later. All data is latched on the ris-
ing edge of WE# or CE#, whichever happens first.
The HY29F002T is automatically set for reading
array data after device power-up and after a hard-
ware reset to ensure that no spurious alteration of
the memory content occurs during the power tran-
sition. No command is necessary in this mode to
obtain array data, and the device remains enabled
for read accesses until the command register con-
tents are altered.
This device features an Erase Suspend mode.
While in this mode, the host may read the array
Rev. 4.1/May 01
5
HYNIX [ HYNIX SEMICONDUCTOR ]
