APCPCWM_4828539:WP_0000001WP_0000001
1
H27(U_S)4G8_6F2D
4 Gbit (512M x 8 bit) NAND Flash
WE
ALE
CLE
RE#
FF
DQ7:0
t
RST
RB#
Figure 29: Reset operation timing
As deꢁined ꢁor
Read
CMD
Cꢂcꢄe Tꢂpe
DOUT
DOUT
D2
CMD
DOUT DOUT
CMD
31ꢇ
ꢈꢈꢈ
31ꢇ
32ꢇ
D2
Dn
DQx
tWB
tWB
tWB
tRR
tRR
tCBSYR
tR
tCBSYR
SR[6]
Figure 30: "sequential" read cache timings, start (and continuation) of cache operation
Rev 1.4 / OCT. 2010
49
B34416/177.179.157.84/2010-10-08 10:08
*ba53f20d-240c*