GMS81C5108
The External Interrupts INT0, INT1 and INT2 can each be
transition-activated (1-to-0, 0-to-1 and both transiton).The
interrupts are controlled by the interrupt master enable flag
I-flag (bit 2 of PSW), the interrupt enable register (IENH,
IENL) and the interrupt request flag (IRQH, IRQL) except
Power-on reset and software BRK interrupt.
contains also a master enable bit, I-flag, which disables all
interrupts at once. When an interrupt is occurred, the I-flag
is cleared and disable any further interrupt, the return ad-
dress and PSW are pushed into the stack and the PC is vec-
tored to. Once in the interrupt service routine the source(s)
of the interrupt can be determined by polling the interrupt
request flag bits.
Interrupt enable registers are shown in Figure 17-2. These
registers are composed of interrupt enable flags of each in-
terrupt source, these flags determine whether an interrupt
will be accepted or not. When enable flag is “0”, a corre-
sponding interrupt source is prohibited. Note that PSW
The interrupt request flag bit(s) must be cleared by soft-
ware before re-enabling interrupts to avoid recursive inter-
rupts. The Interrupt Request flags are able to be read and
written.
IENH (Interrupt Enable High Register)
R/W
R/W
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
Bit :
7
6
5
ADDRESS : 0DB
RESET VALUE : -0000000
H
-
KSE
BITE
INT0E
INT1E
T0E
T1E
INT2E
B
IENL (Interrupt Enable Low Register)
R/W
R/W
R/W
4
R/W
3
Bit :
7
6
5
2
1
0
ADDRESS : 0DA
RESET VALUE : -0000---
H
-
REME
ADE
SIOE
WTE
-
-
-
B
Enables or disables the interrupt individually
If flag is cleared, the interrupt is disabled.
0 : Disable
1 : Enable
IRQH (Interrupt Request High Register)
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
Bit :
7
ADDRESS : 0DD
RESET VALUE : -0000000
H
-
KSIF
BITIF
INT0IF
INT1IF
T0IF
T1IF
INT2IF
B
IRQL (Interrupt Request Low Register)
R/W
R/W
R/W
4
R/W
3
Bit :
7
6
5
2
1
0
ADDRESS : 0DC
RESET VALUE : -0000---
H
-
REMIF
ADIF
SIOIF
WTIF
-
-
-
B
Shows the interrupt occurrence
0 : Not occurred
1 : Interrupt request is occurred
Figure 17-2 Interrupt Enable Registers and Interrupt Request Registers
17.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted
or the interrupt latch is cleared to “0” by a reset or an in-
struction. Interrupt acceptance sequence requires 8 fOSC (2
µs at fMAIN=4MHz) after the completion of the current in-
struction execution. The interrupt service task is terminat-
ed upon execution of an interrupt return instruction
[RETI].
interrupts is temporarily disabled.
2. Interrupt request flag for the interrupt source accepted is
cleared to “0”.
3. The contents of the program counter (return address)
and the program status word are saved (pushed) onto the
stack area. The stack pointer decreases 3 times.
4. The entry address of the interrupt service program is
read from the vector table address and the entry address
is loaded to the program counter.
Interrupt acceptance
1. The interrupt master enable flag (I-flag) is cleared to
“0” to temporarily disable the acceptance of any follow-
ing maskable interrupts. When a non-maskable inter-
rupt is accepted, the acceptance of any following
5. The instruction stored at the entry address of the inter-
rupt service program is executed.
66
JUNE 2001 Ver 1.0
HYNIX [ HYNIX SEMICONDUCTOR ]
