GMS81C5108
To accomplish communication, typically three pins are
used:
ting the SIO1 and SIO0 and the transfer clock rate is decid-
ed by setting the SICK1 and SICK0 of SCI Mode Control
Register as shown in Figure 16-1. And the polarity of
transfer clock is selected by setting the POL. The MSBS
bit is used to select which bit would be sending or receiv-
ing.
- Serial Data In
- Serial Data Out
- Serial Clock
R07/SI
R06/SO
R05/SCK
The serial data transfer operation mode is decided by set-
Port Selection
SIO1
SIO0
Function Selection
R05/SCK
R05
R06/SO
R06
R07/SI
R07
R07
SI
0
0
1
1
0
1
0
1
-
Transmit Mode
Receive Mode
Transmit and Receive
SCK
SO
SCK
R06
SCK
SO
SI
16.1 Data Transmit/Receive Timing
The SCI operation is executed by setting the SIOST bit to
“1”. The SIOST bit is cleared to “0” automatically after 1
machine cycle. The Serial output data is shift in or shift out
at edge decided by POL. Interrupt is occurred when the
eight in/out datas is counted by octal counter.
MSBS=0
SIOST
R05/SCK
(POL=1)
R05/SCK
(POL=0)
D0
D1
D2
D3
D4
D5
D6
D7
R06/SO
R07/SI
SIOSF
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
SIOIF
(SCI Int. Req)
Figure 16-2 SCI Timing Diagram
JUNE 2001 Ver 1.0
63
HYNIX [ HYNIX SEMICONDUCTOR ]
