GMS81C5108
17. INTERRUPTS
The GMS81C5108 interrupt circuits consist of Interrupt
enable register (IENH, IENL), Interrupt request flag
(IRQH, IRQL), Interrupt Edge Selection Register (IESR),
priority circuit and Master enable flag (“I” flag of PSW).
The configuration of interrupt circuit is shown in Figure
17-1 and Interrupt priority is shown in Table 17-1 .
ed by BITIF which is set by overflow of the Basic Interval
Timer Register (BITR).
Reset/Interrupt
Symbol Priority Vector Addr.
Hardware Reset
Key Scan Interrupt
BIT Interrupt
External Interrupt 0
External Interrupt 1
Timer 0 Interrupt
Timer 1 Interrupt
External Interrupt 2
Remocon Interrupt
AD Interrupt
RESET
KS
BIT
INT0
INT1
T0
-
1
2
3
4
5
6
7
8
FFFEH
FFFCH
FFFAH
FFF8H
FFF6H
FFF4H
FFF2H
FFF0H
FFEEH
FFECH
FFEAH
FFE8H
The flags that actually generate these interrupts are bit
INT0F, INT1F and INT2F in Register IRQH. When an ex-
ternal interrupt is generated, the flag that generated it is
cleared by the hardware when the service routine is vec-
tored to only if the interrupt was transition-activated.
T1
INT2
REM
AD
SIO
WT
The Timer 0 and Timer 2 Interrupts are generated by T0IF
and T1IF, which are set by a match in their respective tim-
er/counter register. The AD converter Interrupt is generat-
ed by ADIF which is set by finishing the analog to digital
conversion. The Basic Interval Timer Interrupt is generat-
9
10
11
SIO Interrupt
Watch Timer Interrupt
Table 17-1 Interrupt Priority
Internal bus line
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction.When it goes interrupt service,
I-flag is cleared by hardware, thus any other
Interrupt Enable
Register (Higher byte)
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
IENH
IRQH
“1” by hardware.
6
KSIF
Key Scan
5
BIT
BITIF
INT0IF
INT1IF
TOIF
4
3
2
1
0
Ext. Int. 0
Ext. Int. 1
Release STOP
IESR
Timer 0
Timer 1
To CPU
T1IF
Ext. Int. 2
INT2IF
I Flag
Interrupt Master
Enable Flag
Interrupt
Vector
Address
Generator
6
5
Remocon
REMIF
A/D Converter
SIO
ADIF
4
3
SIOIF
WT
WTIF
Interrupt Enable
Register (Lower byte)
IRQL
IENL
Internal bus line
Figure 17-1 Block Diagram of Interrupt Function
JUNE 2001 Ver 1.0
65
HYNIX [ HYNIX SEMICONDUCTOR ]
