GMS81C5108
17.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction,
which has the lowest priority order.
Interrupt vector address of BRK is shared with the vector
of TCALL 0 (Refer to Program Memory Section). When
BRK interrupt is generated, B-flag of PSW is set to distin-
guish BRK from TCALL 0.
=0
B-FLAG
=1
BRK or
TCALL0
BRK
INTERRUPT
ROUTINE
TCALL0
ROUTINE
Each processing step is determined by B-flag as shown in
Figure 17-4.
RETI
RET
Figure 17-4 Execution of BRK/TCALL0
17.3 Multi Interrupt
If two requests of different priority levels are received si-
multaneously, the request of higher priority level is ser-
viced. If requests of the interrupt are received at the same
time simultaneously, an internal polling sequence deter-
mines by hardware which request is serviced.
.
Main Program
service
TIMER 1
service
INT0
service
However, multiple processing through software for special
features is possible. Generally when an interrupt is accept-
ed, the I-flag is cleared to disable any further interrupt. But
as user sets I-flag in interrupt routine, some further inter-
rupt can be serviced even if certain interrupt is in progress.
enable INT0
disable other
EI
Occur
TIMER1 interrupt
Occur
INT0
Example: Even though Timer1 interrupt is in progress,
INT0 interrupt serviced without any suspend.
enable INT0
enable other
TIMER1: PUSH
A
PUSH
PUSH
LDM
LDM
EI
X
Y
IENH,#80H
IENL,#0
;Enable INT0 only
;Disable other
;Enable Interrupt
:
In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable "EI" in the TIMER1 routine.
:
:
:
:
:
Figure 17-5 Execution of Multi Interrupt
LDM
LDM
POP
POP
POP
RETI
IENH,#0FFH ;Enable all interrupts
IENL,#0F0H
Y
X
A
68
JUNE 2001 Ver 1.0
HYNIX [ HYNIX SEMICONDUCTOR ]
