GMS81C5108
16. Serial Communication Interface
The SCI module allows 8-bits of data to be synchronously
transmitted and received. This is useful for communication
with other peripheral of microcontroller devices.This con-
sists of serial I/O data register, serial I/O mode register,
clock selection circuit octal counter and control circuit as
shown in Figure 16-1.
SIOM (Seriol I/O Mode Register)
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
7
Bit :
ADDRESS : 0FE
RESET VALUE : 00000001
H
POL
MSBS
SIO1
SIO0
SICK1
SICK0
SIOST
SIOSF
B
POL (Polarity Selection)
0 : Data Transmission at falling edge
MSBS (MSB First Transmit and Receive Selection)
0 : LSB First
(Received data latch at rising edge)
1 : Data Transmission at rising edge
(Received data latch at falling edge)
1 : MSB First
SICK[1:0] (Serial I/O Clock Source Selection)
00: fMAIN ÷4 or fSUB ÷4
SIO[1:0] (Serial I/O Operation Mode)
00 : Normal Port (R05, R06, R07)
01: fMAIN ÷16 or fSUB ÷16
10: T0O (Timer 0 Output)
01 : Transmit Mode (SCK, SO, R07)
10 : Receive Mode (SCK, R06, SI)
11 : Transmit & Receive Mode (SCK, SO, SI)
11: External Clock
SIOSF (Serial I/O Status Flag)
0 : During SIO Operation
SIOST (Serial I/O Operation Start Control)
0 : SIO Operation Stop
1 : SIO Operation Finished
1 : SIO Operation Start
(After one SCK clock become “0”)
SIOD (Serial I/O Data Register)
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
7
Bit :
ADDRESS : 0FF
RESET VALUE : Undefined
H
SIOD7
SIOD6
SIOD5
SIOD4
SIOD3
SIOD2
SIOD1
SIOD0
SCMR[1:0]
SICK[1:0]
2
2
2
2
4
f
MAIN÷2 or fSUB÷2
POL
SIOST
Start
X
00
01
10
11
IN
IN
0X
1X
Pre-
scaler
4
f
MAIN÷2 or fSUB÷2
Complete
SIOSF
Clear
SX
SIO Control Circuit
T0OV(Timer 0 Overflow)
Clock
Shift Clock
SIO
Interrupt
R05 SCK
Octal Counter
(3-Bit)
SIOIF
SIO[1:0] = 00
1
SCK
SICK[1:0] ≠ 11
& SIO[1:0] ≠ 00
MSBS
MSB
LSB
0
1
0
1
SIOD(8-Bit)
SIO Data Register
R06/SO
R07/SI
SIO[1] = 1
SIO[0] = 1
MSBS
Figure 16-1 SCI Registers and Block Diagram
62
JUNE 2001 Ver 1.0
HYNIX [ HYNIX SEMICONDUCTOR ]
