GMS81C5108
17.4 External Interrupt
The external interrupt on INT0, INT1 and INT2 pins are
edge triggered depending on the edge selection register
IESR (address 0D8H) as shown in Figure 17-6.
Example: To use as an INT0 and INT2
:
:
The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, and both edge.
;**** Set port as an input port R0
LDM
;
R0DR,#1111_1010B
;**** Set port as an interrupt port
LDM
;
PMR,#0000_0101B
;**** Set Falling-edge Detection
INT0
INT1
INT0IF
INT1IF
LDM
:
:
:
IESR,#0001_0001B
INT0 INTERRUPT
INT1 INTERRUPT
Response Time
The INT0, INT1 and INT2 edge are latched into INT0F,
INT1F and INT2F at every machine cycle. The values are
not actually polled by the circuitry until the next machine
cycle. If a request is active and conditions are right for it to
be acknowledged, a hardware subroutine call to the re-
quested service routine will be the next instruction to be
executed. The DIV itself takes twelve cycles. Thus, a max-
imum of twelve complete machine cycles elapse between
activation of an external interrupt request and the begin-
ning of execution of the first instruction of the service rou-
tine.
INT2
INT2IF
INT2 INTERRUPT
IESR
[0D8 ]
H
IESR (Ext. Interrupt Edge Selection Register)
Interrupt Edge Selection Register)
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
Bit :
7
6
Interrupt response timings are shown in Figure 17-7.
-
-
INT21 INT20 INT11 INT10 INT01 INT00
ADDRESS : 0D8
RESET VALUE : --000000
INT2[1:0] (INT2 Edge Selections)
00 : Int. Disable
01 : Falling (1-to-0 transition)
10 : Rising (0-to-1 transition)
11 : Both (Rising & Falling)
H
B
INT1[1:0] (INT1 Edge Selection)
00 : Int. Disable
01 : Falling (1-to-0 transition)
10 : Rising (0-to-1 transition)
11 : Both (Rising & Falling)
INT0[1:0] (INT0 Edge Selections)
00 : Int. Disable
01 : Falling (1-to-0 transition)
10 : Rising (0-to-1 transition)
11 : Both (Rising & Falling)
Figure 17-6 External Interrupt Block Diagram
max. 12 f
8 f
OSC
OSC
Interrupt
latched
Interrupt
goes
active
Interrupt
processing
Interrupt
routine
Figure 17-7 Interrupt Response Timing Diagram
JUNE 2001 Ver 1.0
69
HYNIX [ HYNIX SEMICONDUCTOR ]
