GMS81C5108
to noise on pins AVDD and AN0 to AN3. Since the effect
increases in proportion to the output impedance of the an-
alog input source, it is recommended that a capacitor is
connected externally as shown below in order to reduce
noise.
ENABLE A/D CONVERTER
A/D INPUT CHANNEL SELECT
ANALOG REFERENCE SELECT
A/D START (ADST = 1)
Analog
AN0~AN3
Input
100~1000pF
Figure 14-3 Analog Input Pin Connecting Capacitor
NOP
(3) Pins AN0/R20 to AN3/R23
NO
The analog input pins AN0 to AN3 also function as input/
output port (PORT R2) pins. When A/D conversion is per-
formed with any of pins AN0 to AN3 selected, be sure not
to execute a PORT input instruction while conversion is in
progress, as this may reduce the conversion resolution.
ADF = 1
YES
READ ADDR
Also, if digital pulses are applied to a pin adjacent to the
pin in the process of A/D conversion, the expected A/D
conversion value may not be obtainable due to coupling
noise. Therefore, avoid applying pulses to pins adjacent to
the pin undergoing A/D conversion.
Figure 14-2 A/D Converter Operation Flow
A/D Converter Cautions
(1) Input range of AN0 to AN3
(4) AVDD pin input impedance
The input voltages of AN0 to AN3 should be within the
specification range. In particular, if a voltage above AVDD
or below VSS is input (even if within the absolute maxi-
mum rating range), the conversion value for that channel
can not be indeterminated. The conversion values of the
other channels may also be affected.
A series resistor string of approximately 10KΩ is connect-
ed between the AVDD pin and the VSS pin.
Therefore, if the output impedance of the reference voltage
source is high, this will result in parallel connection to the
series resistor string between the AVDD pin and the VSS
pin, and there will be a large reference voltage error.
(2) Noise countermeasures
In order to maintain 8-bit resolution, attention must be paid
JUNE 2001 Ver 1.0
59
HYNIX [ HYNIX SEMICONDUCTOR ]
