GMS81C5108
14. ANALOG TO DIGITAL CONVERTER
The analog-to-digital converter (A/D) allows conversion
of an analog input signal to a corresponding 8-bit digital
value. The A/D module has four analog inputs, which are
multiplexed into one sample and hold. The output of the
sample and hold is the input into the converter, which gen-
erates the result via successive approximation. The analog
supply voltage is connected to AVDD of ladder resistance
of A/D module.
setting input mode by R2DR direction register. And select
the corresponding channel to be converted by setting
ADAN[1:0].
The processing of conversion is start when the start bit
ADST is set to “1”. After one cycle, it is cleared by hard-
ware. The register ADDR contains the result of the A/D
conversion. When the conversion is completed, the result
is loaded into the ADDR, the A/D conversion status bit
ADF is set to “1”, and the A/D interrupt flag ADIF is set.
The block diagram of the A/D module is shown in Figure
14-1. The A/D status bit ADF is automatically set when A/
D conversion is completed, cleared when A/D conversion
is in process. The conversion time takes maximum 30 uS
(at fMAIN = 4MHz).
The A/D module has two registers which are the A/D mode
register (ADMR) and A/D data register (ADDR). The
ADMR register, shown in Figure 14-1, controls the opera-
tion of the A/D converter module. The port pins can be
configured as analog inputs or digital I/O. To use analog
inputs, each port should be assigned analog input port by
ADAN[1:0]
A/D Converter
Data Register
ANEN
11
ADDRESS : 0ED
RESET VALUE : Undefined
H
R23/AN3
ADDR (8-bit)
ANEN
10
Sample & Hold
S/H
R22/AN2
R21/AN1
R20/AN0
Comparator
ANEN
ANEN
Successive
Approximation
Circuit
A/D Interrupt
ADIF
01
00
Resistor
Ladder
Circuit
ANEN
AV
DD
ADMR (A/D Mode Register)
R/W
6
R/W
3
R/W
2
R/W
1
R
0
Bit :
7
-
5
4
ADDRESS : 0EC
H
ADEN
-
-
ADAN1
ADAN0
ADST
ADF
RESET VALUE : -0--0001
B
ADAN[1:0] (A/D Converter Input Selection)
00 : Channel 0 (R20/AN0)
ADEN (A/D Converter Enable bit)
1 : Enable
0 : Disable
01 : Channel 1 (R21/AN1)
10 : Channel 2 (R22/AN2)
ADST (A/D Start bit)
1 : A/D Conversion is started
After 1 cycle, cleared to “0”
0 : Bit force to zero
11 : Channel 3 (R23/AN3)
ADF (A/D Status bit)
0 : A/D Conversion is in process
1 : A/D Conversion is completed
ADDR (A/D Data Register)
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
Bit :
ADDRESS : 0ED
RESET VALUE : Undefined
H
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
Figure 14-1 A/D Converter Block Diagram & Registers
58
JUNE 2001 Ver 1.0
HYNIX [ HYNIX SEMICONDUCTOR ]
