GMS81C5108
13. Watch Timer/Watch Dog Timer
This has two functions, one is the interrupt occurrence for
watch time and the other is the signal generation of
WDTOUTB for watch dog.
13.1 Watch Timer
The watch timer consists of the clock selector, 21-bit bina-
ry counter and watch timer mode register. It is a multi-pur-
pose timer. It is generally used for watch design.
clock source, if the CPU enters into stop mode, the main-
clock is stopped and then watch timer is also stopped. If the
sub-clock is the source clock, the watch timer count cannot
be stopped. Therefore, the sub-clock does not stop but con-
tinues to oscillate even when the CPU is in the STOP
mode. The timer counter consists of 21-bit binary counter
and it can count to max 64 seconds at sub-clock.
The bit 1,2 of WTMR select the clock source of watch tim-
er among sub-clock, fMAIN÷27 of main-clock and fMAIN of
main-clock. The fMAIN of main-clock is used usually for
watch timer test, so generally it is not used for the clock
source of watch timer. The fMAIN÷27 of main-clock is used
when the single clock system is organized. In fMAIN÷27
The bit 2, 3 of WTMR select the interrupt request interval
of watch timer among 2Hz, 4Hz, 16Hz and 1/64Hz.
WTMR (Watch Timer Mode Register)
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
Bit :
7
-
ADDRESS: 0EF
INITIAL VALUE:-0000000
H
WTEN WDTEN WDTCL WTIN1 WTIN0 WTCK1 WTCK0
B
WTEN (Watch Timer Enable Bit)
0: Watch Timer Disable
WDTEN (Watch Dog Timer Enable Bit)
0: Watch Dog Timer Disable
1: Watch Timer Enable
1: Watch Dog Timer Enable
WTIN[1:0] (Watch Timer Interrupt Interval Selection)
00: 16Hz
WDTCL (Watch Dog Timer Clear Bit)
0: Timer running
01:
4Hz
1: WDT Clear (Auto reset after 1 cycle)
10:
11: 1/64Hz
2Hz
WTCK[1:0] (Watch Timer Clock Source Selection)
00: Sub. Clock (f
)
SUB
7
01: Main Clock (f
10: Main Clock (f
11: -
÷2 )
MAIN
MAIN
)
* When f
= 32.768 kHz and f
= 4.19 MHz
SUB
MAIN
Figure 13-1 Watch Timer Mode Register
WTIN[1:0]
WTCK[1:0]
16 Hz
4 Hz
2 Hz
1/64 Hz
Watch Timer
Interrupt
f
f
f
SUB
21 BIT
7
MAIN÷2
MAIN
MUX
MUX
WTIF
Binary Counter
WDTOUT
WTEN
2 Bit
F/F
WDTEN
WDTCL
Figure 13-2 Watch Timer Block Diagram
56
JUNE 2001 Ver 1.0
HYNIX [ HYNIX SEMICONDUCTOR ]
