GMS81C5108
fxin
T1
00
01
02
03
04
7F
80
81
3FF
00
01
02
PWM
POL=1
PWM
POL=0
Duty Cycle [80 +1 x 250nS = 32.25uS]
H
Period Cycle [3FF x 250nS = 256uS, 3.9kHz]
H
T1CK[1:0] = 00 (250nS)
PWMHR = 0C
T1PPR (8-bit)
PWM03 PWM02
Period
H
1
1
FF
H
T1PPR = FF
H
T1PDR (8-bit)
80
PWM01 PWM00
Duty
T1PDR = 80
H
0
0
H
Figure 12-12 Example of PWM at 4MHz
T1CK[1:0] = 10 (2uS)
PW M HR = 00H
T1PPR = 0DH
Write T1PPR to 09
Period changed
H
T1PDR = 04H
Source
clock
T1
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 00 01 02 03 04 05 06 07 08 09 00 01 02 03 04
PWM
POL=1
Duty Cycle
[04 +1 x 2uS = 10uS]
Duty Cycle
Duty Cycle
H
[04 +1 x 2uS = 10uS]
[04 +1 x 2uS = 10uS]
H
H
Period Cycle [0D +1 x 2uS = 28uS, 35.7kHz]
H
Period Cycle [09 +1 x 2uS = 20uS, 50kHz]
H
Figure 12-13 Example of Changing the Period in Absolute Duty Cycle (@4MHz)
Example:
Timer1 @4Mhz, 4kHz - 20% duty PWM mode
LDM R3DR,#0000_XX1XB
LDM TM1,#0010_0000B
;R31 output
;pwm enable
LDM T1PWHR,#0000_1100B ;20% duty
LDM T1PPR,#1110_0111B ;period 250uS
LDM T1PDR,#1100_0111B ;duty 50uS
LDM RSR,#X1XX_XXXXB
LDM TM1,#0010_0011B
;set pwm port.
;timer1 start
X means don’t care
JUNE 2001 Ver 1.0
55
HYNIX [ HYNIX SEMICONDUCTOR ]
