GMS81C5108
PWM Period = [PWMHR[3:2]T1PPR+1] X Source Clock
PWM Duty = [PWMHR[1:0]T1PDR+1] X Source Clock
less PWM output. In Figure 12-11, the duty data is trans-
ferred from the master to the slave when the period data
matched to the counted value. (i.e. at the beginning of next
duty cycle).
If it needed more higher frequency of PWM, it should be
reduced resolution.
The bit POL0 of TM1 decides the polarity of duty cycle.
Note: If the duty value and the period value are same, the
PWM output is determined by the bit POL0 (1: High,
0: Low). And if the duty value is set to “00H”, the
PWM output is determined by the bit POL0(1: Low,
0: High). The period value must be same or more
than the duty value, and 00H cannot be used as the
period value.
The duty value can be changed when the PWM outputs.
However the changed duty value is output after the current
period is over. And it can be maintained the duty value at
present output when changed only period value shown as
Figure 12-13. As it were, the absolute duty time is not
changed in varying frequency.
Note: If the user need to change mode from the Timer1
mode to the PWM mode, the Timer1 should be
stopped firstly, and then set period and duty register
value. If user writes register values and changes
mode to PWM mode while Timer1 is in operation,
the PWM data would be different from expected
data in the beginning.
Frequency
Resolution
T1CK[1:0]
T1CK[1:0]
T1CK[1:0]
=10 (2uS)
=00 (250nS) =01 (500nS)
10-bit
9-bit
8-bit
7-bit
3.9KHz
7.8KHz
1.95KHz
3.9KHz
7.8KHz
15.6KHz
0.49KHZ
0.98KHZ
1.95KHz
3.90KHz
15.6KHz
31.25KHz
The relation of frequency and resolution is in inverse pro-
portion. Table 12-2 shows the relation of PWM frequency
vs. resolution.
Table 12-2 PWM Frequency vs. Resolution at 4MHz
ADDRESS : 0E2
RESET VALUE : 00
H
POL
X
16BIT
0
PWME
1
CAP1
0
T1CK1
X
T1CK0
X
T1CN
X
T1ST
X
TM1
H
ADDRESS : 0E5
RESET VALUE : ----0000
H
PWMHR
-
-
-
-
PWM03 PWM02 PWM01 PWM00
B
Bit Manipulation Not Available
X
X
X
X
Period High
PWMHR[3:2]
Duty High
X : The value “0” or “1” corresponding your operation.
T1ST
T1PPR (8-bit)
T0 clock source
0 : Stop
1 : Clear and Start
COMPARATOR
R31/PWM
S
R
Q
CLEAR
1
MUX
T1 (8-bit)
PWMO
[PMR.6]
÷ 1
÷ 2
÷ 8
X
0X
1X
IN
POL
COMPARATOR
SX
IN
T1CN
Slave
2
T1CK[1:0]
SCMR[1:0]
T1PDR (8-bit)
PWMHR[1:0]
Master
T1PDR (8-bit)
Figure 12-11 PWM Mode
54
JUNE 2001 Ver 1.0
HYNIX [ HYNIX SEMICONDUCTOR ]
