GMS81C5108
TM0 (Timer0 Mode Register)
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
Bit :
7
-
6
-
ADDRESS: 0E0
INITIAL VALUE:--000000
H
CAP0
T0CK2 T0CK1 T0CK0
T0CN
T0ST
B
Reserved
CAP0 (Capture Mode Selection Bit)
0: Capture Disable
1: Capture Enable
T0CK[2:0] (Timer 0 Input Clock Selection)
000: fMAIN÷2 or fSUB÷2
2
2
001: fMAIN÷2 or fSUB÷2
3
3
010: fMAIN÷2 or fSUB÷2
T0CN (Timer 0 Continue Start)
0: Stop Counting
1: Start Counting
5
5
011: fMAIN÷2 or fSUB÷2
f
f
: main-clock frequency
: sub-clock frequency
MAIN
7
7
100: fMAIN÷2 or fSUB÷2
SUB
9
9
101: fMAIN÷2 or fSUB÷2
10
10
or fSUB÷2
110: fMAIN÷2
T0ST (Timer 0 Start Control)
0: stop counting
111: External Event clock (EC0)
1: clear the counter and start count again
TM1 (Timer1 Mode Register)
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
Bit :
ADDRESS: 0E2
INITIAL VALUE:00000000
H
POL
16BIT
PWME
CAP1
T1CK1 T1CK0
T1CN
T1ST
B
POL (PWM Output Polarity Selection)
0: Duty Active Low
1: Duty Active High
T1CK[1:0] (Timer 1 Input Clock Selection)
00: f
01: f
or f
MAIN
SUB
÷2 or f ÷2
MAIN
SUB
3
3
10: fMAIN÷2 or fSUB÷2
16BIT (16 Bit Mode Selection)
0: 8-Bit Mode
11: Timer 0 Clock
1: 16-Bit Mode
T1CN (Timer 1 Continue Start)
0: Stop Counting
1: Start Counting
PWME (PWM Enable Bit)
0: PWM Disable
1: PWM Enable
T1ST (Timer 1 Start Control)
0: stop counting
1: clear the counter and start count again
CAP1 (Capture Mode Selection Bit)
0: Capture Disable
1: Capture Enable
**The counter will be cleared and restarted only when the TxST bit cleared and set again.
If TxST bit set again when TxST bit is set, the counter can’t be cleared but only start again.
Figure 12-1 Timer0,1 Registers
46
JUNE 2001 Ver 1.0
HYNIX [ HYNIX SEMICONDUCTOR ]
