GMS81C5108
CDR0 (Input Capture Register)
T0 (Timer 0 Counter Register)
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
Bit :
ADDRESS: E1
INITIAL VALUE:00H
H
CDR07 CDR06 CDR05 CDR04 CDR03 CDR02 CDR01 CDR00
In Timer mode, this register is the value of Timer 0 counter and in Capture mode, this register is the value of input capture.
TDR0 (Timer 0 Data Register)
W
7
W
6
W
5
W
4
W
3
W
2
W
1
W
0
Bit :
ADDRESS: 0E1
INITIAL VALUE:FF
H
TDR07 TDR06 TDR05 TDR04 TDR03 TDR02 TDR01 TDR00
If the counter of Timer 0 and the data of TDR0 is equal, interrupt is occurred.
H
CDR1 (Input Capture Register)
T1 (Timer 1 Counter Register)
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
Bit :
ADDRESS: 0E4
INITIAL VALUE:00
H
CDR17 CDR16 CDR15 CDR14 CDR13 CDR12 CDR11 CDR10
H
In Timer mode, this register is the value of Timer 1 counter and in Capture mode, this register is the value of input capture.
TDR1 (Timer 1 Data Register)
W
7
W
6
W
5
W
4
W
3
W
2
W
1
W
0
Bit :
ADDRESS: 0E3
INITIAL VALUE:FF
H
TDR17 TDR16 TDR15 TDR14 TDR13 TDR12 TDR11 TDR10
If the counter of Timer 1 and the data of TDR1 is equal, interrupt is occurred.
H
H
H
T1PPR (Timer 1 Pulse Period Register)
W
7
W
6
W
5
W
4
W
3
W
2
W
1
W
0
Bit :
ADDRESS: 0E3
INITIAL VALUE:FF
H
T1PPR7 T1PPR6 T1PPR5 T1PPR4 T1PPR3 T1PPR2 T1PPR1 T1PPR0
The period is decided by PWM.
T1PDR (Timer 1 Pulse Duty Register)
W/R
7
W/R
6
W/R
5
W/R
4
W/R
3
W/R
2
W/R
1
W/R
0
Bit :
ADDRESS: 0E4
INITIAL VALUE:00
H
T1PDR7 T1PDR6 T1PDR5 T1PDR4 T1PDR3 T1PDR2 T1PDR1 T1PDR0
In PWM mode, decide the pulse duty.
PWMHR (PWM High Register)
W
3
W
2
W
1
W
0
Bit :
7
-
6
-
5
-
4
-
ADDRESS: 0E5
H
PWM03 PWM02 PWM01 PWM00
INITIAL VALUE:----0000
B
Reserved
PWM Period = [PWMHR[3:2] + T1PPR] x Source Clock
PWM Duty = [PWMHR[1:0] + T1PDR] x Source Clock
Figure 12-2 Related Registers with Timer/Counter
JUNE 2001 Ver 1.0
47
HYNIX [ HYNIX SEMICONDUCTOR ]
