GMS81C5108
11. BASIC INTERVAL TIMER
The GMS81C5108 has one 8-bit Basic Interval Timer that
is free-run and can not stop. Block diagram is shown in
Figure 11-1.
interrupt to be generated. The Basic Interval Timer is con-
trolled by the clock control register (CKCTLR) shown in
Figure 11-2.
The Basic Interval Timer Register (BITR) is increased ev-
ery internal count pulse which is divided by prescaler.
Since prescaler has divided ratio by 8 to 1024, the count
rate is 1/8 to 1/1024 of the oscillator frequency. After reset,
the BCK bits are all set, so the longest oscillation stabiliza-
tion time is obtained.
Source clock can be selected by lower 3 bits of CKCTLR.
When write “1” to bit BCL of CKCTLR, BITR register is
cleared to “0” and restart to count up. The bit BCL be-
comes “0” automatically after one machine cycle by hard-
ware.
BITR and CKCTLR are located at same address, and ad-
dress 0F4H is read as a BITR, and written to CKCTLR.
It also provides a Basic interval timer interrupt (BITF).
The count overflow of BITR from FFH to 00H causes the
3
3
4
5
6
7
8
f
f
f
f
f
f
MAIN÷2 or fSUB÷2
4
MAIN÷2 or fSUB÷2
8-bit up-counter
BITR
5
MAIN÷2 or fSUB÷2
source
clock
overflow
6
MAIN÷2 or fSUB÷2
Basic Interval Timer Interrupt
BITF
MUX
7
MAIN÷2 or fSUB÷2
8
MAIN÷2 or fSUB÷2
[0F4 ]
H
9
9
f
f
MAIN÷2 or fSUB÷2
10
10
clear
MAIN÷2 or fSUB÷2
Select Input clock
BCK<2:0>
3
BCL
f
f
: main-clock frequency
: sub-clock frequency
MAIN
CKCTLR
[0F4 ]
H
SUB
Basic Interval Timer
clock control register
Internal bus line
Figure 11-1 Block Diagram of Basic Interval Timer
Source clock
Interrupt (overflow) Period
BCK
<2:0>
SCMR[1:0]=
SCMR[1:0]=
10 or 11
At fMAIN=4MHz
At fSUB=32.768kHz
00 or 01
f
f
f
f
f
f
f
f
MAIN÷23
MAIN÷24
MAIN÷25
MAIN÷26
MAIN÷27
MAIN÷28
MAIN÷29
MAIN÷210
f
f
f
f
f
f
f
f
SUB÷23
SUB÷24
SUB÷25
SUB÷26
SUB÷27
SUB÷28
SUB÷29
SUB÷210
000
001
010
011
100
101
110
111
0.512 ms
1.024
62.5 ms
125.0
2.048
250.0
4.096
500.0
8.192
1000.0
2000.0
4000.0
8000.0
16.384
32.768
65.536
Table 11-1 Basic Interval Timer Interrupt Time
JUNE 2001 Ver 1.0
43