GMS81C5108
12.2 16 Bit Timer/Counter Mode
The Timer register is running with 16 bits. A 16-bit timer/
counter register T0, T1 are increased from 0000H until it
matches TDR0, TDR1 and then resets to 0000H. The
match output generates Timer 0 interrupt not Timer 1 in-
terrupt.
The clock source of the Timer 0 is selected either internal
or external clock by bit T0CK2, T0CK1 and T0CK0.
In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1
should be set to “1” respectively.
ADDRESS : 0E0
RESET VALUE : --000000
H
TM0
TM1
-
-
CAP0
0
T0CK2
X
T0CK1
X
T0CK0
X
T0CN
X
T0ST
X
B
ADDRESS : 0E2
H
POL
X
16BIT
1
PWME
0
CAP1
0
T1CK1
1
T1CK0
1
T1CN
X
T1ST
X
RESET VALUE : 00000000
B
X : The value “0” or “1” corresponding your operation.
T0ST
T0CK[2:0]
0 : Stop
1 : Clear and Start
Edge Detector
EC0
1
T1 (8-bit)
T0 (8-bit)
CLEAR
MUX
÷ 2
÷ 4
÷ 8
X
0X
1X
IN
TIMER 0
INTERRUPT
T0CN
T0IF
÷ 32
÷ 128
÷ 512
÷ 1024
SX
IN
COMPARATOR
2
F/F
TDR1 (8-bit)
TDR0 (8-bit)
SCMR[1:0]
COMPO (R31)
PWMO
[PMR.6]
Figure 12-6 16-bit Timer / Counter Mode
12.3 8-Bit Capture Mode
The Timer 0 capture mode is set by bit CAP0 of timer
mode register TM0 (bit CAP1 of timer mode register TM1
for Timer 1) as shown in Figure 12-7.
flow occurrence.
Timer/Counter still does the above, but with the added fea-
ture that a edge transition at external input INTx pin causes
the current value in the Timer x register (T0,T1), to be cap-
tured into registers CDRx (CDR0, CDR1), respectively.
After captured, Timer x register is cleared and restarts by
hardware.
As mentioned above, not only Timer 0 but Timer 1 can also
be used as a capture mode.
The Timer/Counter register is increased in response inter-
nal or external input. This counting function is same with
normal timer mode, and Timer interrupt is generated when
timer register T0 (T1) increases and matches TDR0
(TDR1).
It has three transition modes: “falling edge”, “rising edge”,
“both edge” which are selected by interrupt edge selection
register IESR (Refer to External interrupt section). In addi-
tion, the transition at INTx pin generate an interrupt.
This timer interrupt in capture mode is very useful when
the pulse width of captured signal is more wider than the
maximum period of Timer.
Note: The CDR0, TDR0 and T0 are in same address. In
the capture mode, reading operation is read the
CDR0 and in timer mode, reading operation is read
the T0. TDR0 is only for writing operation.
For example, in Figure 12-9, the pulse width of captured
signal is wider than the timer data value (FFH) over 2
times. When external interrupt is occurred, the captured
value (13H) is more little than wanted value. It can be ob-
tained correct value by counting the number of timer over-
The CDR1, T1 are in same address, the TDR1 is lo-
cated in different address. In the capture mode,
reading operation is read the CDR1
50
JUNE 2001 Ver 1.0
HYNIX [ HYNIX SEMICONDUCTOR ]
