GMS81C5108
These timers have each 8-bit count register and data regis-
ter. The count register is increased by every internal or ex-
ternal clock input. The internal clock has a prescaler divide
ratio option of 2, 4, 8, 32,128, 512, 1024 (selected by con-
trol bits T0CK2, T0CK1 and T0CK0 of register TM0) and
1, 2, 8 (selected by control bits T1CK1 and T1CK0 of reg-
ister TM1).
In counter function, the counter is increased every 0-to 1
(rising edge) transition of EC0 pin. In order to use counter
function, the bit R03 of the R0 Direction Register (R0DR)
should be set to “0” and the bit EC0 of Port Mode Register
(PMR) should set to “1”. The Timer 0 can be used as a
counter by pin EC0 input, but Timer 1 can not used as a
counter.
In the Timer, timer register TX increases from 00H until it
matches TDRX and then reset to 00H. If the value of TX is
equal with TDRX, Timer X interrupt is occurred (latched in
TXIF bit). TDR0 and T0 register are in same address, so
this register is read from T0 and written to TDR0.
Note: The contents of TDR0 and TDR1 must be initialized
(by software) with the value between 1H and 0FFH,
not 0H.
TDR0
n
n-1
P
CP
9
8
7
6
5
4
3
2
1
0
TIME
Interrupt period
= P x (n+1)
CP
Timer 0 (T0IF)
Interrupt
Occur interrupt
Occur interrupt
Occur interrupt
Figure 12-4 Counting Example of Timer Data Registers
TDR0
enable
disable
clear & start
stop
TIME
Timer 0 (T0IF)
Interrupt
Occur interrupt
Occur interrupt
T0ST
Start & Stop
T0ST = 1
T0ST = 0
T0CN
Control count
T0CN = 0
T0CN = 1
Figure 12-5 Timer Count Operation
JUNE 2001 Ver 1.0
49
HYNIX [ HYNIX SEMICONDUCTOR ]
