GMS81C5108
7
-
6
-
5
4
-
3
2
1
0
ADDRESS: 0F4
INITIAL VALUE: ----0111
H
-
BCL BCK2 BCK1 BCK0
CKCTLR
B
Basic Interval Timer source clock select
3
3
000: fMAIN÷2 or fSUB÷2
4
4
001: fMAIN÷2 or fSUB÷2
5
5
f
f
: main-clock frequency
: sub-clock frequency
MAIN
010: fMAIN÷2 or fSUB÷2
6
6
011: fMAIN÷2 or fSUB÷2
SUB
7
7
100: fMAIN÷2 or fSUB÷2
Caution:
8
8
101: fMAIN÷2 or fSUB÷2
9
9
or fSUB÷2
110: fMAIN÷2
Both register are in same address,
when write, to be a CKCTLR,
when read, to be a BITR.
10
10
111: fMAIN÷2 or fSUB÷2
Clear bit
0: Normal operation (free-run)
1: Clear 8-bit counter (BITR) to "0". This bit becomes 0 automatically
after one machine cycle.
7
6
5
4
3
2
1
0
ADDRESS: 0F4
H
BITR
INITIAL VALUE: 00
H
8-BIT BINARY COUNTER
Figure 11-2 BITR: Basic Interval Timer Mode Register
Example 1
:
Interrupt request flag is generated every 8.192ms at 4MHz.
:
LDM
CKCTLR,#0CH
SET1 BITE
EI
:
44
JUNE 2001 Ver 1.0
HYNIX [ HYNIX SEMICONDUCTOR ]
