GMS81C5108
STOP Mode
ing program execution. In Stop mode, the on-chip main-
frequency oscillator, system clock, and peripheral clock
are stopped (Watch timer clock is oscillating continuous-
ly:. With the clock frozen, all functions are stopped, but the
on-chip RAM and Control registers are held. The port pins
output the values held by their respective port data register,
the port direction registers. The status of peripherals during
Stop mode is shown below.
For applications where power consumption is a critical
factor, device provides STOP mode for reducing power
consumption.
Start The Stop Operation
The STOP mode can be entered by STOP instruction dur-
Peripheral
CPU
STOP Mode
All CPU operations are disabled
Retain
Sleep Mode
All CPU operations are disabled
Retain
RAM
LCD driver
Basic Interval Timer
Operates continuously
Halted
Operates continuously
Operates continuously
Halted (Only when the Event counter mode
is enabled, Timer 0,1 operates normally)
Timer/Event counter 0,1
Timer/Event counter 0,1 operates continuously
Watch Timer
Key Scan
Operates continuously
Active
Operates continuously
Active
Oscillation1
Oscillation
Retain
Stop (XIN=L, XOUT=L)
Oscillation
Main-oscillation
Sub-oscillation
I/O ports
Retain
Control Registers
Retain
Retain
by RESET, Key Scan interrupt,
Release method
SIO interrupt, Watch Timer interrupt,
Timer interrupt (EC0), and External interrupt
by RESET, All interrupts
Table 10-1 Peripheral Operation during Power Saving Mode
1. refer to the Table 10-2
Operating
Clock source
Main
Operating Mode
Main
Sleep Mode
Sub
Sub
Sleep Mode
Stop Mode
Operating Mode
SCMR<1:0>
00,01,10 → Oscillation
11 → Stop
SCMR<1:0>
00,01,10 → Oscillation
11 → Stop
Main Clock
Oscillation
Oscillation
Stop
Sub Clock
System Clock
Peri. Clock
Oscillation
Active
Oscillation
Stop
Oscillation
Active
Oscillation
Stop
Oscillation
Stop
Active
Active
Active
Active
Stop
Table 10-2 Clock Operation of STOP and SLEEP mode
is not reduced before the Stop mode is invoked, and that
VDD is restored to its normal operating level before the
Stop mode is terminated.
Note: Since the XIN pin is connected internally to GND to
avoid current leakage due to the crystal oscillator in STOP
mode, do not use STOP instruction when an external clock
is used as the main system clock.
The reset should not be activated before VDD is restored to
its normal operating level, and must be held active long
enough to allow the oscillator to restart and stabilize.
And after STOP instruction, at least two or more NOP in-
struction should be written as shown in example below.
In the Stop mode of operation, VDD can be reduced to min-
imize power consumption. Be careful, however, that VDD
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JUNE 2001 Ver 1.0
HYNIX [ HYNIX SEMICONDUCTOR ]
