GMS81C5108
Example)
:
To release STOP mode, corresponding interrupt should be
enabled before STOP mode.
Specially as a clock source of Timer/Event counter, EC0
pin can release it by Timer/Event counterꢁInterrupt re-
questꢂ
LDM
STOP
NOP
NOP
:
CKCTLR,#0000_1111B
The Interval Timer Register CKCTLR should be initial-
ized by software in order that oscillation stabilization time
should be longer than 20ms before STOP mode.
Reset redefines all the control registers but does not change
the on-chip RAM. External interrupts allow both on-chip
RAM and Control registers to retain their values.
Release the STOP mode
Start-up is performed to acquire the time for stabilizing os-
cillation. During the start-up, the internal operations are all
stopped.
The exit from STOP mode is using hardware reset or exter-
nal interrupt, watch timer, SIO interrupt, key scan or timer
interrupt (EC0).
Oscillator
(X pin)
IN
Internal Clock
External Interrupt
STOP Instruction
Executed
BIT Counter
n
n+2
1
0
n+1
0
FE
1
2
n+3
FF
Clear
Normal Operation
Stop Operation
Normal Operation
t
ST
> 20ms
by software
Before executing Stop instruction, Basic Interval Timer must be set
properly by software to get stabilization time which is longer than 20ms.
Figure 10-8 STOP Mode Release Timing by External Interrupt
Oscillator
(X pin)
IN
Internal Clock
RESET
STOP Instruction
Executed
BIT Counter
n
n+2 n+3
1
0
n+1
0
FE
1
2
n+4
Stop Operation
FF
Clear
Normal Operation
Normal Operation
t
> 62.5ms
ST
at 4.19MHz by hardware
1
t
ST
=
x 256
f
÷1024
MAIN
Figure 10-9 STOP Mode Release Timing by RESET
JUNE 2001 Ver 1.0
41
HYNIX [ HYNIX SEMICONDUCTOR ]
