GMS81C5108
10.1 Operation Mode
The system clock controller starts or stops the main-fre-
quency clock oscillator and switches between the sub fre-
quency clock. The operating mode is generally divided
into the main active mode and the sub active mode, which
are controlled by System clock mode register (SCMR).
Figure 10-3 shows the operating mode transition diagram.
Sub Active mode
This mode is low-frequency operating mode
In this mode, the CPU and the peripheral hardware clock
are provided by low-frequency clock oscillation, so power
consumption can be reduced.
System clock control is performed by the system clock
mode register, SCMR. During reset, this register is initial-
ized to “0” so that the main-clock operating mode is select-
ed.
SLEEP mode
In this mode, the CPU clock stops while peripherals and
the oscillation source continue to operate normally.
STOP mode
Main Active mode
In this mode, the system operations are all stopped, holding
the internal states valid immediately before the stop at the
low power consumption level.
This mode is fast-frequency operating mode.
The CPU and the peripheral hardwares are operated on the
high-frequency clock. At reset release, this mode is in-
voked.
Main : Oscillation
Sub : Oscillation
System Clock : Sub
Main : Oscillation
Sub : Oscillation
System Clock : Main
SET1 SCMR.1
Main Active
Sub Active
Mode 1
Mode
CLR1 SCMR.1
* Note1 : Stop released by
Reset, Key Scan
Watch Timer interrupt
Timer interrupt (event counter)
SIO (External clock)
External interrupt
* Note2 : Sleep released by
Reset, Key Scan
All interrupts
* Note3 : this is sequential
1) CLR1 SCMR.0
2) Oscillation stabilation time (more than 65ms)
3) CLR1 SCMR.1
- Sub clock cannot be stopped by STOP instruction.
* Note1 / * Note2
Sub Active
Mode 2
Stop / Sleep
Mode
STOP / SET1 SMR.0
Main : Stop or Oscillation (case of **1)
Sub : Oscillation
System Clock : Stop
Main : Stop
Sub : Oscillation
System Clock : Sub
Figure 10-3 Operating Mode
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JUNE 2001 Ver 1.0
HYNIX [ HYNIX SEMICONDUCTOR ]
