Chapter 5. Interrupt
5.3.2 Interrupt Timing
CLOCK
A command before interrupt
interrupt process step
SYNC
Interrupt Request Sampling
Fig. 5.2 Interrupt Enable Accept Timing
Maximum 12 machine cycle (When execute DIV instruction)
Minimum 0 machine cycle
Interrupt Request
sampling time
Interrupt preprocess step is 8 machine cycle
Maximum 1 + 12 + 8 = 21 machine cycle
Interrupt overhead
Minimum 1 + 0 + 8 = 9 machine cycle
5.3.3 The valid timing after executing Interrupt control instructions
I flag is valid just after executing of EI/DI on the contrary.
Interrupt Enable register is valid one instruction after controlling interrupt Enable
Register.
5 - 5
HYNIX [ HYNIX SEMICONDUCTOR ]
