Chapter 5. Interrupt
Clock
Interrupt Process Step
ISR*1
SYNC
R/W
INTERNAL
ADDR. BUS
PC
SP
SP-1
SP-2
LVA*2
HVA*3
NEW PC
INTERNAL
DATA BUS
OP
CODE
OP
CODE
¡ È ¡ È
VECTOR VECTOR
¡ È ¡ È
H
L
PCH
PCL
PSW
INTERNAL
READ
INTERNAL
WRITE
Fig. 5. 3 Interrupt Procesing Step Timing
*1 ISR : Interrupt Service Routine
*2 LVA : Low Vector Address
*3 HVA : High Vector Address
5.1 SOFTWARE INTERRUPT
5.5.1 Interrupt by Break(BRK) Instruction
¡ È
¡ È
Software interrupt is available just by writing Break(BRK) instruction.
The values of PC and PSW is stacked by BRK instruction and then B flag of PSW is set
and I flag is reset.
Flag change by BRK execution
N
N
V
V
G
G
B
H
I
Z
Z
C
C
PSW
PSW
set
1
reset
0
H
(Right after BRK execution)
5 - 7
HYNIX [ HYNIX SEMICONDUCTOR ]
