Chapter 5. Interrupt
5.3 INTERRUPT ACCEPT MODE
The interrupt priority order is determined by bit(IM1, IM0) of IMOD register.
Interrupt Mode Register
7
0
-
-
IM1
IM0
IP3
IP2
IP1
IP0
IMOD
R/W <00CAH>
Assigning by interrupt accept mode bit
IM1
IM0
Priority
Fixed by H/W
0
0
1
0
1
*
Changeable by IP 3-0
Interrupt is inhibited
5.3.1 Selection of interrupt by IP3 - IP0
The condition allow for accepting interrupt is set state of the interrupt mask enable flag
¡ È ¡ È
and the interrupt enable bit must be
1 .
IP3
IP2
IP1
IP0
Selection interrupt
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
KSCNR (Key Scan)
INT1R (External interrupt 1)
INT2R (External interrupt 2)
Reserved
T0R (Timer 0)
T1R (Timer 1)
T2R (Timer 2)
Reserved
Reserved
WDTR (Watch Dog Timer)
BITR (Basic Interval Timer)
Reserved
Table 5.2 Interrupt Selection by IP3 - IP0
¡ È ¡ È
0 .
*In Reset state, these IP3 - IP0 registers become all
5 - 4
HYNIX [ HYNIX SEMICONDUCTOR ]
