Chapter 5. Interrupt
Interrupt vector of BRK instruction is shared by vector of Table Call(TCALL0). When
both instruction of BRK and TCALL0 are used, as shown in Fig. 5.4 each processing
routine is judged by contents of B flag.
There is no instruction to reset directly B flag.
0
B flag
1
BRK or
TCALL0
BRK INTERRUPT ROUTINE
TCALL0 ROUTINE
RET
RETI
Fig. 5.4 Execution of BRK or TCALL0
5.6 MULTIPLE INTERRUPT
If there is an interrupt, Interrupt Mask Enable Flag is automatically cleared before
entering the Interrupt Service Routine. After then, no interrupt is accepted. If EI
¡ È ¡ È
, and each enable bit
instruction is executed, interrupt mask enable bit becomes
1
can accept interrupt request. When two or more interrupts are generated
simultaneously, the highest priority interrupt set by Interrupt Mode Register is accepted.
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HYNIX [ HYNIX SEMICONDUCTOR ]
