Chapter 5. Interrupt
Internal Data Bus
0
7
0
7
0
7
-
-
-
-
-
-
-
-
-
-
IENL
IENH
IMOD
KSCNR
INT1R
INT2R
T0R
KSCN
INT1
INT2
PRIORITY
CONTROL
IFT0
T1R
IFT1
INT.
VECTOR
ADDR.
T2R
IFT2
WDTR
IFWDT
IFBIT
BITR
IRQ
BRK
Standby Mode Release
Fig. 5.1 Interrupt Source
Mask
Priority
Interrupt Source
RST (RESET PIN)
INT Vector H INT Vector L
Non-maskable
-
FFFF
FFFB
FFF9
FFF7
FFF3
FFF1
FFEF
FFE9
FFE7
FFDF
FFFE
FFFA
FFF8
FFF6
FFF2
FFF0
FFEE
FFE8
FFE6
FFDE
0
1
2
3
4
5
6
7
-
KSCNR (Key Scan)
INT1R(External Interrupt 1)
INT2R(External Interrupt 2)
T0R(Timer0)
Hardware
Interrupt
Maskable
T1R(Timer1)
T2R(Timer2)
WDTR (Watch Dog Timer)
BITR (Basic Interval Timer)
BRK Instruction
Software
Interrupt
-
Table 5.1 Interrupt Source
5 - 2
HYNIX [ HYNIX SEMICONDUCTOR ]
