Chapter 4. Peripheral Hardware
7
0
-
-
WDTON
ENPCK
BTCL
BTS2
BTS1
BTS0
CKCTLR
W <00C7H>
BTS2
BTS1
BTS0
B.I.T. Input clock
PS3 (2us)
Standby release time
512 us
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PS4 (4us)
1,024 us
PS5 (8us)
2,048 us
PS6 (16us)
PS7 (32us)
PS8 (64us)
PS9 (128us)
PS10 (256us)
4,096 us
8,192 us
16,384 us
32,768 us
65,536 us
Table 4.1 Standby release time according to BTS
4.1.4.3 Reading Basic Interval Timer
By reading of the Basic Interval Timer Register(BITR), we can read counter value of
B.I.T. Because B.I.T can be cleared or read, the spending time up to maximum 65.5ms
can be available. B.I.T is read-only register. If B.I.T register is written, then CKCTLR
register with same address is written.
Basic Interval Timer Register
7
0
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
BITR
R <00C7H>
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HYNIX [ HYNIX SEMICONDUCTOR ]
