Chapter 4. Peripheral Hardware
4.1.2 Prescaler
Prescaler consists of 12-bit binary counter. The clock supplied from oscillation circuit is
input to prescaler (fex). The divided output from each bit of prescaler is provided to
peripheral hardware.
4.1.3 Peripheral hardware clock control
Clock to peripheral hardware can be stopped by bit4 (ENPCK) of CKCTLR Register.
¡ È ¡ È
ENPCK is set to
1
in reset state.
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9 PS10 PS11 PS12
fex
ENPCK
B.I.T
PS0
fcpu
PS1
PS2
PS3
PS4
PS5
PS6
PS7 PS8
PS9
PS10 PS11 PS12
Peripheral
fex(MHz)
Freq
PS0
PS1
2M
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9 PS10 PS11 PS12
4M
1M
1u
500K
2u
250K
4u
125K
8u
62.5K 31.25K 15.63K 7.183K 3.906K 1.953K 0.976K
4
2
Period(s)
Freq
250n 500n
16u
32u
64u 128u 256u 512u 1024u
2M
1M
1u
500k
2u
250K
4u
125K
8u
62.5K 31.25K 15.63K 7.183K 3.906K 1.953K 0.976K 0.488K
Period(s)
500n
16u
32u
64u 128u 256u 512u 1024u 2048u
Fig. 4.3 Block diagram of Prescaler
4 - 3
HYNIX [ HYNIX SEMICONDUCTOR ]
