Chapter 4. Peripheral Hardware
7
0
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WDTON
ENPCK
BTCL
BTS2
BTS1
BTS0
CKCTLR
W <00C7H>
Max. Interval of WDT
output (*note1)
BTS2
BTS1
BTS0
Input clock of WDT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
512 us
1,024 us
2,048 us
4,096 us
8,192 us
16,384 us
32,768 us
65,536 us
32,756 us
64,512 us
129,024 us
258,048 us
516,096 us
1,032,192 us
2,064,384 us
4,128,768 us
*note1) When WDTR Register value is 63(3FH)
¡ È ¡ È
0 for WDTR Register value.
Caution : Do not use
Device come into the reset state by WDT
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